公开(公告)号：DE69836943T2

公开(公告)日：2008-02-14

申请号：DE69836943

申请日：1998-09-29

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： VARIAN KATHRYN H ,  TOBBEN DIRK ,  SENDELBACH MATTHEW

IPC: H01L21/302 ,  H01L21/3105 ,  H01L21/3065 ,  H01L21/3205 ,  H01L21/762 ,  H01L21/768 ,  H01L23/522

Abstract: A substantially planar surface is produced from a non-conformal device layer formed over a complex topography, which includes narrow features with narrow gaps and wide features and wide gaps. A conformal layer is deposited over the non-conformal layer. The surface is then polished to expose the non-conformal layer over the wide features. An etch selective to the non-conformal layer is then used to substantially remove the non-conformal layer over the wide features. The conformal layer is then removed, exposing the non-conformal layer. The thickness of the non-conformal layer is now more uniform as compared to before. This enables the polish to produce a planar surface with reduced dishing in the wide spaces.

公开(公告)号：DE69836943D1

公开(公告)日：2007-03-15

申请号：DE69836943

申请日：1998-09-29

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： VARIAN KATHRYN H ,  TOBBEN DIRK ,  SENDELBACH MATTHEW

IPC: H01L21/302 ,  H01L21/3105 ,  H01L21/3065 ,  H01L21/3205 ,  H01L21/762 ,  H01L21/768 ,  H01L23/522

Abstract: A substantially planar surface is produced from a non-conformal device layer formed over a complex topography, which includes narrow features with narrow gaps and wide features and wide gaps. A conformal layer is deposited over the non-conformal layer. The surface is then polished to expose the non-conformal layer over the wide features. An etch selective to the non-conformal layer is then used to substantially remove the non-conformal layer over the wide features. The conformal layer is then removed, exposing the non-conformal layer. The thickness of the non-conformal layer is now more uniform as compared to before. This enables the polish to produce a planar surface with reduced dishing in the wide spaces.

公开(公告)号：DE69826934D1

公开(公告)日：2004-11-18

申请号：DE69826934

申请日：1998-06-05

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GUTSCHE MARTIN ,  TOBBEN DIRK

IPC: H01L21/28 ,  H01L21/768

Abstract: A method for manufacturing a dual damascene structure includes the use of a sacrificial stud (12) and provides an improved defined edge on the interface between the conductive line openings (9) and the via openings (11).

公开(公告)号：DE69834686D1

公开(公告)日：2006-07-06

申请号：DE69834686

申请日：1998-03-17

Applicant: INFINEON TECHNOLOGIES AG

Inventor： TOBBEN DIRK ,  SPULER BRUNO ,  GUTSCHE MARTIN ,  WEIGAND PETER

IPC: H01L21/768 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/3213 ,  H01L23/12 ,  H05K1/00 ,  H05K3/06 ,  H05K3/22 ,  H05K3/24

Abstract: A method for forming a plurality of electrically conductive wires on a substrate. The method includes forming a relatively non-planar metal layer over a surface of the substrate. A self-planarizing material is deposited over the metal layer. The self-planarizing material forms a planarization layer over the surface of the metal layer. The planarization layer has a surface relatively planar compared to the relatively non-planar metal layer. A photoresist layer is deposited over the surface of the planarization layer. The photoresist layer is patterned with a plurality of grooves to form a mask with such grooves exposing underling portions of the planarization layer. The photoresist mask is used as a mask to etch grooves in the exposed portions of the planarization layer and thereby form a second mask. The second mask exposes underling portions of the relatively non-planar metal layer. The second mask is used to etch grooves in the relatively non-planar conductive metal layer and thereby form the plurality of electrically conductive wires in the metal layer. The wires are separated from each other by the grooves formed in the relatively non-planar metal layer. The planarization layer is formed by a spinning-on an organic polymer, for example an organic polymer having silicon, or a flowable oxide, or a hydrogensilsequioxane, or divinyl-siloxane-benzocyclobutene. The metal layer is etched using reactive ion etching. The planarization layer is removed using a wet chemical etch.

公开(公告)号：DE10240405A1

公开(公告)日：2003-05-28

申请号：DE10240405

申请日：2002-09-02

Applicant: INFINEON TECHNOLOGIES AG

Inventor： TOBBEN DIRK ,  BRINTZINGER AXEL ,  WEBER STEFAN

IPC: H01L23/525 ,  H01L21/768 ,  H01L21/8242

Abstract: An antifuse (e.g., 130) is formed in an integrated circuit through the use of a block mask (e.g., photoresist 120) during in situ antifuse dielectric formation. Generally, the mask allows self-aligned oxidation of an oxidizable metal (e.g., aluminum 104) to form the antifuse dielectric (e.g., aluminum oxide 124), while preventing oxidation of non-programmable or fixed connections (e.g., conductive stack 128). The number of mask, deposition, or etching steps may be reduced relative to prior art methods. In addition, a fixed connection may be formed during the formation of and at the same level as the antifuse link.

公开(公告)号：DE69835180T2

公开(公告)日：2007-06-14

申请号：DE69835180

申请日：1998-03-17

Applicant: INFINEON TECHNOLOGIES AG

Inventor： TOBBEN DIRK ,  WEIGAND PETER

IPC: H01L27/04 ,  H01L27/108 ,  B81B3/00 ,  H01L21/02 ,  H01L21/32 ,  H01L21/822 ,  H01L21/8242

Abstract: A method for forming a microstructure includes photolithographically forming a vertically extending post on a portion of a surface of a substrate to provide a first structure. A flowable, sacrificial material is deposited over a surface of the first structure. The flowable, sacrificial materially flows off the top surface and sidewall portions of the post onto adjacent portions of the surface of the substrate to provide a second structure. A non-sacrificial material is deposited over a surface of the second structure. The non-sacrificial material is deposited to conform to the surface of the second structure. The non-sacrificial is deposited over the sacrificial material, over the sidewall portions and over the top surface of the post. The deposited sacrificial material is selectively removed while the non-sacrificial material remains to form a third structure with a horizontal member provided by the non-sacrificial material. The horizontal member is supported a predetermined distance above the surface of the substrate by a lower portion of the post. The flowable material is a flowable oxide, for example, hydrogensilsesquioxane glass, and the post has a width less than 20 mu m. The resulting structure, formed with a single photolithographic step, is used for supporting a capacitor deposited over it. The capacitor is formed as a sequence of deposition steps; i.e., depositing a first conductive layer over a surface of the support structure; depositing a dielectric layer over the conductive layer; and depositing a second conductive layer over the dielectric layer.

公开(公告)号：DE69826934T2

公开(公告)日：2005-10-13

申请号：DE69826934

申请日：1998-06-05

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GUTSCHE MARTIN ,  TOBBEN DIRK

IPC: H01L21/28 ,  H01L21/768

Abstract: A method for manufacturing a dual damascene structure includes the use of a sacrificial stud (12) and provides an improved defined edge on the interface between the conductive line openings (9) and the via openings (11).

公开(公告)号：DE69932472T2

公开(公告)日：2007-02-15

申请号：DE69932472

申请日：1999-05-31

Applicant: INFINEON TECHNOLOGIES AG

Inventor： TOBBEN DIRK ,  WEBER STEFAN J ,  BRINTZINGER AXEL

IPC: H01L21/768 ,  H01L21/82 ,  H01L23/525

Abstract: A method for forming a semiconductor integrated circuit having a fuse and an active device. A dielectric layer is formed over the fuse and over a contract region of the active device. Via holes are formed through selected regions of the dielectric layer exposing underlying portions of the fuse and underlying portions of a contact region of the active device. An electrically conductive material is deposited over the dielectric layer and through the via holes onto exposed portions of the fuse and the contact region. Portions of the electrically conductive material deposited onto the fuse are selectively removed while leaving portions of the electrically conductive material deposited onto the contact region of the active device. A fill material is disposed in the one of the fuse, a bottom portion of such filling material being spaced from the fuse.

公开(公告)号：DE69834686T2

公开(公告)日：2007-05-31

申请号：DE69834686

申请日：1998-03-17

Applicant: INFINEON TECHNOLOGIES AG

Inventor： TOBBEN DIRK ,  SPULER BRUNO ,  GUTSCHE MARTIN ,  WEIGAND PETER

IPC: H01L21/768 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/3213 ,  H01L23/12 ,  H05K1/00 ,  H05K3/06 ,  H05K3/22 ,  H05K3/24

Abstract: A method for forming a plurality of electrically conductive wires on a substrate. The method includes forming a relatively non-planar metal layer over a surface of the substrate. A self-planarizing material is deposited over the metal layer. The self-planarizing material forms a planarization layer over the surface of the metal layer. The planarization layer has a surface relatively planar compared to the relatively non-planar metal layer. A photoresist layer is deposited over the surface of the planarization layer. The photoresist layer is patterned with a plurality of grooves to form a mask with such grooves exposing underling portions of the planarization layer. The photoresist mask is used as a mask to etch grooves in the exposed portions of the planarization layer and thereby form a second mask. The second mask exposes underling portions of the relatively non-planar metal layer. The second mask is used to etch grooves in the relatively non-planar conductive metal layer and thereby form the plurality of electrically conductive wires in the metal layer. The wires are separated from each other by the grooves formed in the relatively non-planar metal layer. The planarization layer is formed by a spinning-on an organic polymer, for example an organic polymer having silicon, or a flowable oxide, or a hydrogensilsequioxane, or divinyl-siloxane-benzocyclobutene. The metal layer is etched using reactive ion etching. The planarization layer is removed using a wet chemical etch.

公开(公告)号：DE69932472D1

公开(公告)日：2006-09-07

申请号：DE69932472

申请日：1999-05-31

Applicant: INFINEON TECHNOLOGIES AG

Inventor： TOBBEN DIRK ,  WEBER STEFAN J ,  BRINTZINGER AXEL

IPC: H01L21/768 ,  H01L21/82 ,  H01L23/525

Abstract: A method for forming a semiconductor integrated circuit having a fuse and an active device. A dielectric layer is formed over the fuse and over a contract region of the active device. Via holes are formed through selected regions of the dielectric layer exposing underlying portions of the fuse and underlying portions of a contact region of the active device. An electrically conductive material is deposited over the dielectric layer and through the via holes onto exposed portions of the fuse and the contact region. Portions of the electrically conductive material deposited onto the fuse are selectively removed while leaving portions of the electrically conductive material deposited onto the contact region of the active device. A fill material is disposed in the one of the fuse, a bottom portion of such filling material being spaced from the fuse.