公开(公告)号：WO0188977A3

公开(公告)日：2002-06-13

申请号：PCT/US0115759

申请日：2001-05-15

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： MANDELMAN JACK A ,  DIVAKARARUNI RAMA ,  SRINIVASAN RADHIKA ,  HO HERBERT ,  BEINTNER JOACHEN ,  LI YUJUN ,  LAROSA GIUSEPPE

IPC: H01L21/762

CPC classification number: H01L21/76229 ,  H01L21/76224

Abstract: A semiconductor device and method of manufacturing thereof are provided. A trench is formed in a semiconductor substrate. A thin oxide liner is preferably formed on surfaces of the trench. A nitride liner is formed in the trench. Charge is trapped in the nitride liner. In a preferred embodiment, the trench is filled with an oxide by an HDP process to increase the amount of charge trapped in the nitride liner. Preferably, the oxide fill is formed directly on the nitride liner.

Abstract translation: 提供半导体器件及其制造方法。 在半导体衬底中形成沟槽。 优选在沟槽的表面上形成薄的氧化物衬垫。 氮化物衬垫形成在沟槽中。 电荷被困在氮化物衬垫中。 在优选实施例中，沟槽通过HDP工艺填充氧化物以增加在氮化物衬垫中捕获的电荷量。 优选地，氧化物填充物直接形成在氮化物衬垫上。

公开(公告)号：AT457081T

公开(公告)日：2010-02-15

申请号：AT01988335

申请日：2001-12-19

Applicant: IBM ,  INFINEON TECHNOLOGIES CORP

Inventor： BOETTCHER STEVEN ,  HO HERBERT ,  HOINKIS MARK ,  LEE HYUN ,  WANG YUN-YU ,  WONG KWONG

IPC: C23C16/34 ,  H01L21/768 ,  H01L21/3205 ,  H01L23/52 ,  H01L23/532

Abstract: In integrated circuits having copper interconnect and low-k interlayer dielectrics, a problem of open circuits after heat treatment was discovered and solved by the use of a first liner layer of Ti, followed by a conformal liner layer of CVD TiN, followed in turn by a final liner layer of Ta or TaN, thus improving adhesion between the via and the underlying copper layer while reducing the increase in resistance caused by alloying between the Ti and the Copper to an acceptable amount.

公开(公告)号：EP1869709A4

公开(公告)日：2008-07-16

申请号：EP06749815

申请日：2006-04-12

Applicant: IBM

Inventor： MANDELMAN JACK ,  HO HERBERT ,  NING TAK ,  OTANI YOICHI

IPC: H01L21/8247 ,  G11C16/04 ,  H01L27/115 ,  H01L29/792

CPC classification number: H01L27/115 ,  G11C16/0466 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/11568 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/792 ,  H01L29/7926

Abstract: The present invention provides two-transistor silicon-oxide-nitride-oxide-semiconductor (2-Tr SONOS) non-volatile memory cells with randomly accessible storage locations as well as method of fabricating the same, hi one embodiment, a 2-Tr SONOS cell is provided in which the select transistor is located within a trench structure having trench depth from 1 to 2 µm and the memory transistor is located on a surface of a semiconductor substrate adjoining the trench structure. In another embodiment, a 2-Tr SONOS memory cell is provided in which both the select transistor and the memory transistor are located within a trench structure having the depth mentioned above.

公开(公告)号：JPH11297812A

公开(公告)日：1999-10-29

申请号：JP34271998

申请日：1998-12-02

Applicant: IBM ,  TOSHIBA CORP

Inventor： MANDELMAN JACK A ,  MORIKADO MUTSUO ,  HO HERBERT ,  JEFFREY P GANBINO

IPC: H01L21/76 ,  H01L21/762

Abstract: PROBLEM TO BE SOLVED: To inhibit the formation of a recessed part and to prevent the large change of threshold voltage and off current, by previously removing a nitride liner on the upper part of a side wall with shallow trench element separation. SOLUTION: Resist 17 is etched to the depth of 1000 Å from the surface of a silicon substrate by chemical dry etching(CDE). A silicon nitride liner 16a at the upper part of a shallow trench 14 is removed and whole resist 17a in the shallow trench 14 is removed by CDE. TEOS oxide is embedded in the shallow trench 14, and shallow element separation is formed. A pad nitride film 13 and a pad oxide film 12 on a separated element area are removed, and a gate oxide film and a gate electrode are formed. A source area and a drain area are formed by ion implanting and MOSFET is completed. At the time of removing the pad nitride film 13, a recessed part by the removal of the silicon nitride liner is not formed since the silicon nitride liner is not exposed to a surface.

公开(公告)号：JP2000228442A

公开(公告)日：2000-08-15

申请号：JP2000025509

申请日：2000-02-02

Applicant: IBM ,  SIEMENS AG

Inventor： HO HERBERT ,  SRINIVASAN RADHIKA ,  HAMMERL ERWIN ,  AGAHI FARID ,  BRONNER GARY ,  FLIETNER BERTRAND

IPC: H01L21/76 ,  H01L21/762

Abstract: PROBLEM TO BE SOLVED: To reduce parasitic leak of a shallow trench isolation via. SOLUTION: A distance between a silicon nitride liner 43 and an active silicon sidewall is increased by depositing an insulation oxide layer 20 prior to depositing of the silicon nitride liner 43. Preferably, the insulation oxide layer 20 comprises tetraethyl orthosilicate. The method includes formation of one or a plurality of shallow trench isolations inside a semiconductor wafer through etching, sticking of an insulation oxide layer 20 inside a trench, formation of thermal oxide 25 inside a trench and sticking of the silicon nitride liner 43 inside a trench. The thermal oxide 25 can be formed before or after the insulation oxide layer 20 is deposited.

公开(公告)号：WO2006110781A3

公开(公告)日：2007-04-19

申请号：PCT/US2006013561

申请日：2006-04-12

Applicant: IBM ,  MANDELMAN JACK ,  HO HERBERT ,  NING TAK ,  OTANI YOICHI

Inventor： MANDELMAN JACK ,  HO HERBERT ,  NING TAK ,  OTANI YOICHI

IPC: H01L29/76

CPC classification number: H01L27/115 ,  G11C16/0466 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/11568 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/792 ,  H01L29/7926

Abstract: The present invention provides two-transistor silicon-oxide-nitride-oxide-semiconductor (2-Tr SONOS) non-volatile memory cells with randomly accessible storage locations as well as method of fabricating the same, hi one embodiment, a 2-Tr SONOS cell is provided in which the select transistor is located within a trench structure having trench depth from 1 to 2 µm and the memory transistor is located on a surface of a semiconductor substrate adjoining the trench structure. In another embodiment, a 2-Tr SONOS memory cell is provided in which both the select transistor and the memory transistor are located within a trench structure having the depth mentioned above.

Abstract translation: 本发明提供了具有随机访问的存储位置的双晶体管氧化硅 - 氧化物 - 氧化物半导体（2-Tr SONOS）非易失性存储单元及其制造方法。在一个实施例中，2-Tr SONOS 提供了选择晶体管位于具有1至2μm的沟槽深度的沟槽结构内的单元，并且存储晶体管位于与沟槽结构相邻的半导体衬底的表面上。 在另一个实施例中，提供了2-Tr SONOS存储单元，其中选择晶体管和存储晶体管都位于具有上述深度的沟槽结构内。

公开(公告)号：JPH10214889A

公开(公告)日：1998-08-11

申请号：JP2253198

申请日：1998-01-21

Applicant: SIEMENS AG ,  IBM

Inventor： HO HERBERT ,  HAMMERL ERWIN ,  DOBUZINSKY DAVID M ,  PALM J HERBERT ,  FUGARDI STEPHEN ,  AJMERA ATUL ,  MOSEMAN JAMES F ,  RAMAC SAMUEL C

IPC: H01L21/76 ,  H01L21/318

Abstract: PROBLEM TO BE SOLVED: To contain a trapping center with a lower density than before conversion, by depositing an Si3 N4 covering with a specific thickness in an STI structure by the low-pressure chemical vapor deposition method, performing speedy heat annealing under specific conditions immediately after depositing the covering, and converting Si3 N4 from amorphous to a crystal material. SOLUTION: After a shallow trench is etched, a thin thermal oxide with a thickness of approximately 10nm is grown to eliminate an etching damage. Then, an Si3 N4 covering with a thickness of 5-10nm is deposited on the upper surface of an oxide layer in amorphous state at a temperature of 720-780 deg.C in a shallow trench isolation structure(STI). Then, immediately after the covering is deposited, a high-speed heat annealing is executed nearly for 60 seconds at 1,050-1,150 deg.C in pure nitrogen or ammonium and the Si3 N4 covering is converted from the amorphous state to the crystal material state of a low- temperature-hexagonal (d) Si3 N4 phase.

公开(公告)号：JPH10214886A

公开(公告)日：1998-08-11

申请号：JP874398

申请日：1998-01-20

Applicant: IBM ,  SIEMENS AG ,  TOSHIBA CORP

Inventor： BENEDICT JOHN PRESTON ,  DOBUZINSKY DAVID MARK ,  FLAITZ PHILIP LEE ,  HAMMERL ERWIN N ,  HO HERBERT ,  MOSEMAN JAMES F ,  PALM HERBERT ,  YOSHIDA SEIKO ,  TAKATO HIROSHI

IPC: H01L21/76 ,  H01L21/762

Abstract: PROBLEM TO BE SOLVED: To form an effective O2 diffusion barrier by forming a conformal layer that is selected from a group consisting of a double layer that is made of oxide and nitride in a separation groove and on a protection layer, depositing a CVD layer consisting of an oxide-filling material on the layer, and releasing the protection layer and the conformal layer. SOLUTION: A conformal layer 20 with a thickness of approximately 5-15mm being selected from a group consisting of an acid nitride, a double layer consisting of oxide and nitride, and a double layer consisting of acid nitride and nitride is formed on a protection layer (a pad nitride layer 14 and a pad oxide layer 12) and a separation groove (thermal oxide liner) 18. Then, an oxide-filling material 22 such as tetraethylortosilicate with a thickness of 450-500nm is deposited by the CVD supported by ozone, and the oxide-filling material 22 is subjected to anneal treatment and high-density treatment. Then, the conformal layer 20 and the pad nitride layer 14 and the pad oxide layer 12 are released. Then, the oxide-filling material 22 is flattened so that it is flush with the surface of a substrate.

公开(公告)号：AT518240T

公开(公告)日：2011-08-15

申请号：AT00101726

申请日：2000-01-27

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： HO HERBERT ,  SRINIVASAN RADHIKA ,  HAMMERL ERWIN ,  AGAHI FARID ,  BRONNER GARY ,  FLIETNER BERTRAND

IPC: H01L21/76 ,  H01L21/762

Abstract: A reduction in parasitic leakages of shallow trench isolation vias is disclosed wherein the distance between the silicon nitride liner and the active silicon sidewalls is increased by depositing an insulating oxide layer prior to deposition of the silicon nitride liner. Preferably, the insulating oxide layer comprises tetraethylorthosilicate. The method comprises of etching one or more shallow trench isolations into a semiconductor wafer; depositing an insulating oxide layer into the trench; growing a thermal oxide in the trench; and depositing a silicon nitride liner in the trench. The thermal oxide may be grown prior to or after deposition of the insulating oxide layer.

公开(公告)号：DE69632768D1

公开(公告)日：2004-07-29

申请号：DE69632768

申请日：1996-09-04

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： HO HERBERT ,  HAMMERL ERWIN ,  DOBUZINSKY DAVID M ,  PALM J HERBERT ,  FUGARDI STEPHEN ,  AJMERA ATUL ,  MOSEMAN JAMES E ,  RAMAC SAMUEL C

IPC: H01L21/76 ,  H01L21/3105 ,  H01L21/318 ,  H01L21/32 ,  H01L21/762 ,  H01L21/763 ,  H01L21/334

Abstract: Silicon integrated circuits use a crystalline layer of silicon nitride (Si3N4) in shallow trench isolation (STI) structures as an O2-barrier film. The crystalline Si3N4 lowers the density of electron traps as compared with as-deposited, amorphous Si3N4. Further, a larger range of low-pressure chemical-vapor deposited (LPCVD) Si3N4 films can be deposited, providing a larger processing window for thickness controllability. An LPCVD-Si3N4 film is deposited at temperatures of 720 DEG C to 780 DEG C. The deposited film is in an amorphous state. Subsequently, a high-temperatures rapid-thermal anneal in pure nitrogen or ammonia is conducted at 1050 DEG C to 1100 DEG C for 60 seconds.