公开(公告)号：WO02058147A3

公开(公告)日：2003-03-27

申请号：PCT/US0148803

申请日：2001-12-17

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： IYER SUNDAR ,  KOTHANDARAMAN C RAMAN ,  STETTER MICHAEL

IPC: H01L23/525

CPC classification number: H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An improved fuse structure in an integrated circuit IC structure is made by forming a gate stack comprised of layers of polysilicon and a silicide. Subsequent to the formation of the silicide layer 12, an etch stop silicon nitride layer 15 is deposited over the silicide layer. The silicon nitride layer is patterned to expose the silicide layer. A soft passivation layer 18 is deposited over the exposed silicide layer. The soft passivation layer has a low thermal conductivity which confines energy in the silicide layer, minimizing the current needed to program the fuse. The inherent ductility of the soft passivation layer prevents the generation of cracks in the surrounding layers.

Abstract translation: 通过形成由多晶硅层和硅化物层构成的栅极堆叠来形成集成电路IC结构中的改进的熔丝结构。 在形成硅化物层12之后，在硅化物层上沉积蚀刻停止氮化硅层15。 图案化氮化硅层以暴露硅化物层。 软化钝化层18沉积在暴露的硅化物层上。 软钝化层具有低热导率，其将能量限制在硅化物层中，使得对熔丝编程所需的电流最小化。 软钝化层的固有延展性防止周围层产生裂纹。

公开(公告)号：WO0199152A3

公开(公告)日：2002-04-04

申请号：PCT/US0119813

申请日：2001-06-21

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： STETTER MICHAEL ,  GRELLNER FRANK

IPC: H01L27/108

CPC classification number: H01L27/10805 ,  Y10S257/905 ,  Y10S257/907

Abstract: Active areas (24A,24B) of a Dynamic Random Access Memory (DRAM) formed on a semiconductor substrate are defined by buried bit lines (BL1, BL2, BL3) on two sides and by conductors (20) separated from the semiconductor substrate by electrically insulating layers (22) on two other sides. The conductors are electrically biased during operation of the DRAM to cause portions of the semiconductor substrate therebelow to increase in majority carrier concentration and thus to inhibit inversion therof, commonly known as field plate insulation. Each buried bit line is formed in a trench (14) in the semiconductor substrate. Each trench houses a separate bit line and is lined with an electrical insulator (16) and has a conductor (18A) in a bottom portion thereof. Common drain regions (23A) shared by two transistors are coupled to conductors (18A) by means of a conductor (32).

Abstract translation: 形成在半导体衬底上的动态随机存取存储器（DRAM）的有效区域（24A，24B）由两侧的掩埋位线（BL1，BL2，BL3）和由半导体衬底分离的导体（20）由电 绝缘层（22）在另外两侧。 在DRAM的操作期间，导体被电偏置，以使半导体衬底的部分在其中大部分载流子浓度增加，从而抑制反转，通常称为场板绝缘。 每个掩埋位线形成在半导体衬底中的沟槽（14）中。 每个沟槽容纳单独的位线并且衬有电绝缘体（16），并且在其底部具有导体（18A）。 由两个晶体管共享的公共漏极区域（23A）借助于导体（32）耦合到导体（18A）。

公开(公告)号：EP1399958A4

公开(公告)日：2010-08-25

申请号：EP02744765

申请日：2002-06-27

Applicant: IBM ,  INFINEON TECHNOLOGIES CORP

Inventor： BARTH HANS-JOACHIM ,  BURRELL LLYOD G ,  FRIESE GERALD R ,  STETTER MICHAEL

IPC: H01L21/3205 ,  H01L23/525 ,  H01L21/768 ,  H01L21/82 ,  H01L23/52 ,  H01L23/522 ,  H01L27/10

CPC classification number: H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

公开(公告)号：DE10226571A1

公开(公告)日：2003-01-16

申请号：DE10226571

申请日：2002-06-14

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： BARTH HANS JOACHIM ,  BURRELL LLOYD G ,  FRIESE GERALD ,  STETTER MICHAEL

IPC: H01L21/3205 ,  H01L21/768 ,  H01L21/82 ,  H01L23/52 ,  H01L23/522 ,  H01L23/525 ,  H01L27/10

公开(公告)号：WO0199183A3

公开(公告)日：2002-05-16

申请号：PCT/US0119876

申请日：2001-06-21

Applicant: INFINEON TECHNOLOGIES CORP

Inventor： STETTER MICHAEL ,  GRELLNER FRANK

IPC: H01L21/28 ,  H01L21/285 ,  H01L21/336 ,  H01L21/768 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/108 ,  H01L27/11 ,  H01L27/112 ,  H01L29/78

CPC classification number: H01L21/76895 ,  H01L21/28518 ,  H01L27/1104

Abstract: A method and apparatus for forming a direct buried strap for a semiconductor device, in accordance with the present invention, includes forming a gate stack (106) on a semiconductor substrate (102), and forming a protective layer on sidewalls (108) of the gate stack. The protective layer extends horizontally (109) over a portion of the semiconductor substrate adjacent to the gate stack. A conductive layer (112) is formed over the protective layer and in contact with a gate conductor (107) of the gate stack and in contact with a diffusion region (104) formed in the semiconductor substrate adjacent to the gate conductor. A dielectric layer is formed over the conductive layer, and the dielectric layer is patterned to expose a portion of the conductive layer. The portion of the conductive layer which is exposed includes a portion of the conductive layer over the gate conductor and a portion of the substrate adjacent to the gate conductor. The exposed areas of the conductive layer are silicided to form a direct buried strap (120) and a silicided diffusion region (114) in the substrate. The direct buried strap electrically connects the gate conductor to the diffusion region in a same level of the semiconductor device.

Abstract translation: 根据本发明的用于形成用于半导体器件的直埋掩埋带的方法和装置包括在半导体衬底（102）上形成栅极堆叠（106），并在所述半导体衬底的侧壁（108）上形成保护层 门堆叠 保护层在与栅叠层相邻的半导体衬底的一部分上水平延伸（109）。 导电层（112）形成在保护层之上并与栅极堆叠的栅极导体（107）接触并且与形成在与栅极导体相邻的半导体衬底中的扩散区（104）接触。 介电层形成在导电层上，并且电介质层被图案化以暴露导电层的一部分。 暴露的导电层的部分包括在栅极导体上的导电层的一部分和与栅极导体相邻的衬底的一部分。 导电层的暴露区域被硅化以在衬底中形成直接掩埋带（120）和硅化扩散区（114）。 直接掩埋带将半导体器件的栅极导体电连接到扩散区域。

公开(公告)号：WO0223601A3

公开(公告)日：2002-09-06

申请号：PCT/US0126647

申请日：2001-08-27

Applicant: INFINEON TECHNOLOGIES CORP

Inventor： STETTER MICHAEL ,  SCHROEDER UWE PAUL

IPC: H01L21/311 ,  H01L21/027 ,  H01L21/033 ,  H01L21/768

CPC classification number: H01L21/31144

Abstract: A method for forming contact holes, in accordance with the present invention, includes forming a hard mask layer on a dielectric layer, forming an anti-reflection coating of less than or equal to 1000 angstroms in thickness on the hard mask layer, and forming a silicon containing imaging resist layer on the anti-reflection layer. The imaging resist layer is patterned and the anti-reflection coating and the hard mask are etched by employing the imaging resist layer as a mask. The dielectric layer is then etched by employing the hard mask as a mask.

Abstract translation: 根据本发明的形成接触孔的方法包括在电介质层上形成硬掩模层，在硬掩模层上形成小于或等于1000埃的抗反射涂层，并形成 防反射层上含硅成像抗蚀剂层。 对成像抗蚀剂层进行图案化，并使用成像抗蚀剂层作为掩模来蚀刻抗反射涂层和硬掩模。 然后通过使用硬掩模作为掩模来蚀刻介电层。

公开(公告)号：WO0199184A3

公开(公告)日：2002-06-27

申请号：PCT/US0119881

申请日：2001-06-21

Applicant: INFINEON TECHNOLOGIES CORP

Inventor： STETTER MICHAEL ,  KALTALIOGLU ERDEM ,  COWLEY ANDY

IPC: H01L21/768 ,  H01L23/532

CPC classification number: H01L21/76811 ,  H01L21/76813 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2221/1036 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of fabricating an integrated circuit with a dual dielectric structure and utilizes a dual damascene process to fabricate metal interconnection layers. The dual dielectric structure consists of a first insulating layer (24) of conventional dielectric material, and a second insulating layer (26) of a second dielectric material with a low dielectric constant (low-k dielectric material). The first dielectric material is used in regions of the integrated circuit where the superior mechanical properties of conventional dielectric materials will result in maintaining the reliability and mechanical properties of the integrated circuit. The second dielectric material is used in regions of the integrated circuit where the low dielectric constant will result in improved speed of the integrated circuit and reduced electrical coupling between conductors in the integrated circuit. The fabrication of the dual dielectric structure is integrated with a dual damascene metallization process.

Abstract translation: 一种制造具有双电介质结构的集成电路的方法，并利用双镶嵌工艺来制造金属互连层。 双电介质结构由常规介电材料的第一绝缘层（24）和具有低介电常数（低k电介质材料）的第二介电材料的第二绝缘层（26）组成。 第一介电材料用于集成电路的区域，其中传统介电材料的优良机械性能将导致保持集成电路的可靠性和机械性能。 第二介电材料用于集成电路的区域，其中低介电常数将导致集成电路的改进的速度和减小集成电路中的导体之间的电耦合。 双电介质结构的制造与双镶嵌金属化工艺集成。