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    2.
    发明专利
    未知

    公开(公告)号：DE50100686D1

    公开(公告)日：2003-10-30

    申请号：DE50100686

    申请日：2001-01-05

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： EICHFELD HERBERT ,  KLEIN RALF ,  PAULUS CHRISTIAN ,  ROEMER DIRK

    IPC: H03K6/04 ,  H03K19/003

    Abstract: The invention relates to an arrangement (10) and a method for adjusting the slope times of one or more drivers (90) in such a way that the adjustment is essentially independent of external conditions. The invention also relates to a driver circuit. The arrangement (10) is provided with a device (20) for detecting the time history of an output voltage that is output and supplied to a load (12) by means of the driver/s (90). The measured time values are converted into an output voltage value in a device (36) for converting the measured time history of the output voltage. Moreover, a device (40) for generating a reference voltage value is provided. The device (40) is connected to a device (60) for predetermining a desired slope time for the driver/s (90), whereby the slope time is essentially independent of external conditions. A system pulse can be partitioned into differently long rectangular pulses in the device (60) in such a way that the user of the arrangement (10) can select from the group of the rectangular pulses which match certain slope times respectively. The output voltage value and the reference voltage value are compared in a comparing device (50) that is also connected to the driver/s (90) in such a way that the driver/s (90) can be readjusted thereby.

    3.
    发明专利
    未知

    公开(公告)号：DE10346928A1

    公开(公告)日：2004-05-13

    申请号：DE10346928

    申请日：2003-10-09

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： KLEIN RALF ,  LE THOAI-THAI

    IPC: G11C11/4076 ,  H03H11/26 ,  H03K5/00 ,  H03L7/00 ,  H03L7/081

    Abstract: A delay adjustment circuit for decreasing a phase shift between a system clock and a feedback clock from a semiconductor's internal clock. The circuit includes a difference-pulse generator that provides an interim clock 180 degrees out of phase with the feedback clock when the feedback clock is leading the system clock, and equal to the feedback clock otherwise. The difference-pulse generator also provides a difference-pulse signal that is at logic high for a period of time by which the system clock and an inversion of the interim clock are phase shifted. The circuit also includes a delay control unit and a delay unit which delay the interim clock by the period of time. The resulting delayed interim clock, which is 180 degrees out of phase with the system clock, is inverted to provide an internal clock in phase with the system clock.

    4.
    发明专利
    未知

    公开(公告)号：DE10143421A1

    公开(公告)日：2003-04-03

    申请号：DE10143421

    申请日：2001-09-05

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： KLEIN RALF

    IPC: G11C7/10 ,  H03K19/003 ,  G11C11/4063

    Abstract: An output driver circuit includes a delay device disposed between a signal input and a driver device. The input signal to the driver device can be delayed by a predetermined value with the delay device. The signal amplitude of the output signal from the driver device is compared, in a comparison device, with the signal amplitude of a reference signal at a predetermined time. The time delay for the input signal to the driver device is then set on the basis of the comparison result. A method for adjusting a driver device is also provided.

    9.
    发明专利
    未知

    公开(公告)号：DE50004272D1

    公开(公告)日：2003-12-04

    申请号：DE50004272

    申请日：2000-08-23

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： PAULUS CHRISTIAN ,  KLEIN RALF

    IPC: H03K17/00 ,  H03K17/16 ,  H03K19/003

    Abstract: The invention relates to a driver circuit ( 10 ) for integrated circuits comprising at least one input node ( 11 ) for an input signal and at least one output node ( 12 ) for an output signal. One or several, preferably two partial drivers ( 20, 30 ) supply approximately sine-wave shaped current to the load capacity ( 15 ) thereby improving electromagnetic compatibility. A feedback circuit ( 40 ) is also provided. Said feedback circuit consists of one or several evaluation circuits ( 50 ) and one or several feedback capacitors ( 41 ). The evaluation circuits ( 50 ) are connected to the partial drivers ( 20, 30 ) One feedback capacitor ( 41, 42 ) is respectively arranged between an output node ( 12 ) of the driver circuit ( 10 ) and an input node ( 51 ) of an evaluation circuit ( 50 ). An evaluation circuit ( 50 ) is provided via the feedback condenser ( 41, 42 ) between an output node ( 12 ) of the driver circuit and an input node ( 51 ). The edge steepness of the signal i.e. current which is independent of the actual load, can be produced by means of a feedback circuit ( 40 ). The feedback capacitor ( 41 ) can, for example, be embodied as a non-linear capacitor.

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