5.
    发明专利
    未知

    公开(公告)号:DE10032236C2

    公开(公告)日:2002-05-16

    申请号:DE10032236

    申请日:2000-07-03

    Abstract: The circuit generates a control voltage derived from a reference current per differential amplifier acting as a receiver to set the correct operating point. Switching elements for each receiver in a line carrying a current for generating the control voltage are permanently closed in working mode by a trigger signal (EN) to continuously deliver the current and are closed periodically or at discrete times in standby mode by a refresh signal. The circuit generates a control voltage derived from a reference current (IREF) for each differential amplifier (6,7) functioning as a receiver to set the correct operating point. It has switching elements (10-12) for each receiver in a line (13) carrying a current for generating the control voltage and that are permanently closed in working mode by a trigger signal (EN) to continuously deliver the current and that are closed periodically or at discrete times in standby mode by a refresh signal (SRF). Independent claims are also included for the following: a DRAM memory.

    10.
    发明专利
    未知

    公开(公告)号:DE50100988D1

    公开(公告)日:2003-12-24

    申请号:DE50100988

    申请日:2001-06-19

    Abstract: The circuit generates a control voltage derived from a reference current per differential amplifier acting as a receiver to set the correct operating point. Switching elements for each receiver in a line carrying a current for generating the control voltage are permanently closed in working mode by a trigger signal (EN) to continuously deliver the current and are closed periodically or at discrete times in standby mode by a refresh signal. The circuit generates a control voltage derived from a reference current (IREF) for each differential amplifier (6,7) functioning as a receiver to set the correct operating point. It has switching elements (10-12) for each receiver in a line (13) carrying a current for generating the control voltage and that are permanently closed in working mode by a trigger signal (EN) to continuously deliver the current and that are closed periodically or at discrete times in standby mode by a refresh signal (SRF). Independent claims are also included for the following: a DRAM memory.

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