公开(公告)号：JP2006270056A

公开(公告)日：2006-10-05

申请号：JP2006024594

申请日：2006-02-01

Applicant: Infineon Technologies Ag ,  インフィネオン テヒノロギーズ アーゲーInfineon TechnologiesAG

Inventor： ERBEN ELKE ,  SPITZER ANDREAS

IPC: H01L21/318 ,  H01G4/12 ,  H01L21/316 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/108 ,  H01L29/78

CPC classification number: H01L28/40 ,  C23C16/40 ,  H01G4/085 ,  H01G4/1209 ,  H01L21/3141 ,  H01L21/31645 ,  H01L28/56 ,  H01L28/90

Abstract: PROBLEM TO BE SOLVED: To provide a method for manufacturing a polycrystalline dielectric layer and to provide a semiconductor device using the dielectric layer.
SOLUTION: The polycrystalline dielectric layer 20 is made of a first dielectric material comprising oxide or nitride, and a second material which is less than 1 wt.% of the weight of the dielectric layer. To reduce leakage current along a boundary of a particle 21 of the first dielectric material, the second material for forming non-conductive oxide or nitride having enthalpy lower than that of the first dielectric material is comprised, and arranged at the boundary of the particle of the first dielectric material.
COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供一种制造多晶电介质层的方法，并提供使用电介质层的半导体器件。 解决方案：多晶电介质层20由包含氧化物或氮化物的第一介电材料和小于介电层重量的1重量％的第二材料制成。 为了减小沿着第一介电材料的粒子21的边界的泄漏电流，包含用于形成具有低于第一介电材料的焓的非导电氧化物或氮化物的第二材料，并且被布置在颗粒的边界处 第一介电材料。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2002118107A

公开(公告)日：2002-04-19

申请号：JP2001251144

申请日：2001-08-22

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KERSCH ALFRED ,  SPITZER ANDREAS

IPC: C23C16/44 ,  C23C16/40 ,  C23C16/455 ,  C30B25/02 ,  H01L21/205 ,  H01L21/31 ,  H01L21/314 ,  H01L21/316

Abstract: PROBLEM TO BE SOLVED: To provide a method for manufacturing a sufficiently uniform layer regarding layer thickness, stoichiometry, and electrical characteristics, and for manufacturing a ferroelectric or paraelectric solid layer by vapor deposition. SOLUTION: In the method for manufacturing the crystalline solid layer on a substrate by the vapor deposition, at least one assistant other than a departure gas containing the element of the solid layer that can be deposited is introduced into a reaction chamber. In this case, the assistant has a dipole moment, and contains a molecule adhering onto the surface of the substrate having the dipole moment in a vertical direction to the surface of the substrate quickly during a deposition process, thus determining the crystal structure of the solid layer in advance.

公开(公告)号：DE102014117512B4

公开(公告)日：2019-07-11

申请号：DE102014117512

申请日：2014-11-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SPITZER ANDREAS ,  KAMPEN CHRISTIAN ,  KADOW CHRISTOPH

IPC: H01L23/62 ,  H01L23/522 ,  H01L25/16

Abstract: Halbleitervorrichtung, umfassendeine erste Force-Leitung (401), die elektrisch mit einer Metallstruktur (305) in einer äußersten Verdrahtungsschicht (300) verbunden ist, wobei ein Sense-Via (311) sich von der Metallstruktur (305) durch ein äußerstes Zwischenschichtdielektrikum (210) erstreckt;eine erste Sense-Leitung (411), die von der ersten Force-Leitung (401) getrennt und elektrisch mit der Metallstruktur (305) verbunden ist;eine zweite Force-Leitung (402), die elektrisch mit dem Sense-Via (311) über eine Basisoberfläche (311a) des Sense-Vias (311) verbunden ist, wobei die Basisoberfläche (311a) von der Metallstruktur (305) abgewandt und zu einem Halbleiterkörper (100) ausgerichtet ist, der halbleitende Teile von wenigstens einem Halbleiterelement (190) umfasst;eine zweite Sense-Leitung (412), die elektrisch mit dem Sense-Via (311) durch die Basisoberfläche (311a) verbunden ist; undKontaktvias (319), die sich von der Metallstruktur (305) durch das äußerste Zwischenschichtdielektrikum (210) erstrecken und elektrisch mit dem wenigstens einen Halbleiterelement (190) verbunden sind und durch die im eingeschalteten Zustand der Halbleitervorrichtung ein Laststrom fließt.

公开(公告)号：DE102014117512A1

公开(公告)日：2016-06-02

申请号：DE102014117512

申请日：2014-11-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SPITZER ANDREAS ,  KAMPEN CHRISTIAN ,  KADOW CHRISTOPH

IPC: H01L23/62 ,  H01L23/367 ,  H01L23/485 ,  H01L25/16

Abstract: Eine Halbleitervorrichtung (500) umfasst eine erste Force-Leitung (401), die elektrisch mit einer Metallstruktur (305) in einer äußersten Verdrahtungsschicht (300) verbunden ist, wobei sich ein Sense-Via (311) von der Metallstruktur (305) durch ein äußerstes Zwischenschichtdielektrikum (210) erstreckt. Eine erste Sense-Leitung (411) ist von der ersten Force-Leitung (401) getrennt und ist elektrisch mit der Metallstruktur (305) verbunden. Eine zweite Force-Leitung (402) ist elektrisch mit dem Sense-Via (311) durch eine Basisoberfläche (311a) des Sense-Vias (311) verbunden, wobei die Basisoberfläche (311a) von der Metallstruktur (305) abgewandt und zu einem Halbleiterkörper (100) ausgerichtet ist, der halbleitende Teile von wenigstens einem Halbleiterelement (190) umfasst. Eine zweite Sense-Leitung (412) ist elektrisch mit dem Sense-Via (311) durch die Basisoberfläche (311a) verbunden.

公开(公告)号：DE102005057255B4

公开(公告)日：2007-09-20

申请号：DE102005057255

申请日：2005-12-01

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BERNHARDT HENRY ,  HECHT THOMAS ,  STADTMUELLER MICHAEL ,  KIM YEONG KWAN ,  KAPTEYN CHRISTIAN ,  SCHROEDER UWE ,  SPITZER ANDREAS

IPC: H01L27/108 ,  H01L21/8242

Abstract: The capacitor has a first electrode layer (103), a second electrode layer (104,105) and a dielectric intermediate layer (110) between the electrode layers. The dielectric layer contains a high k dielectric and at least one component containing silicon. Independent claims also cover a method of manufacture.

公开(公告)号：DE10143719A1

公开(公告)日：2003-03-27

申请号：DE10143719

申请日：2001-08-31

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SABISCH WINFRIED ,  SPITZER ANDREAS

IPC: H01L21/00 ,  H01L21/683 ,  H01L21/687 ,  H01J37/32 ,  H01L21/3065 ,  H01L21/68

Abstract: The wafer (1) is held in position by an electrostatic chuck (4) against an electrode (3). A focus ring (2) surrounds the wafer. The ring leaves a free space below the section of the wafer which projects outside the chuck and between ring and wafer. To fill this space a positioning device (31) in the form of Elift pinse is provided so that the wafer can be positioned against the focus ring, the position being monitored by a camera. Provision can be made so that the device can also have a small horizontal movement, e.g. approx. 1mm.

公开(公告)号：DE102005057255A1

公开(公告)日：2007-06-14

申请号：DE102005057255

申请日：2005-12-01

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BERNHARDT HENRY ,  HECHT THOMAS ,  STADTMUELLER MICHAEL ,  KIM YEONG KWAN ,  KAPTEYN CHRISTIAN ,  SCHROEDER UWE ,  SPITZER ANDREAS

IPC: H01L27/108 ,  H01L21/8242

Abstract: The capacitor has a first electrode layer (103), a second electrode layer (104,105) and a dielectric intermediate layer (110) between the electrode layers. The dielectric layer contains a high k dielectric and at least one component containing silicon. Independent claims also cover a method of manufacture.

公开(公告)号：DE10256973B4

公开(公告)日：2006-09-28

申请号：DE10256973

申请日：2002-12-05

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SPITZER ANDREAS ,  ENDERS GERHARD

IPC: H01L27/108 ,  G11C11/24 ,  H01L21/8242 ,  H01L27/105 ,  H01L27/12

Abstract: The memory (10) has an array of memory cells (1), each having a memory capacitor (2) and a selection transistor (3) provided on a semiconductor material strut (4) and having 2 source/drain regions (5,6) and at least one gate layer (7,8). The strut is provided on an insulation layer (11) with the source/drain layers at its opposite ends (A,B), the side edges and the upper surface (15) of the strut provided with a gate dielectric layer (9) and a gate electrode layer (16).

公开(公告)号：DE10041698A1

公开(公告)日：2002-03-14

申请号：DE10041698

申请日：2000-08-24

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KERSCH ALFRED ,  SPITZER ANDREAS

IPC: C23C16/44 ,  C23C16/40 ,  C23C16/455 ,  C30B25/02 ,  H01L21/205 ,  H01L21/31 ,  H01L21/314 ,  H01L21/316 ,  H01L21/8239

Abstract: Production of a crystalline solid body layer on a substrate (3) by CVD comprises introducing an auxiliary material (H) into the reaction chamber in addition to the starting gases (P) containing the elements of the solid body layer. The auxiliary material is obtained in such a way that it contains molecules which have a dipole moment and the properties to deposit during the deposition process over a short time on the substrate surface to form the crystal structure of the solid body layer. Preferred Features: The auxiliary material is introduced from an external supply such as a supply vessel. The auxiliary material consists of reaction products of the CVD process pumped from the reaction chamber.

公开(公告)号：DE102004036461A1

公开(公告)日：2006-02-16

申请号：DE102004036461

申请日：2004-07-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： LUYKEN JOHANNES R ,  HOFMANN FRANZ ,  FISCHER BJOERN ,  SPITZER ANDREAS

IPC: G11C11/404 ,  H01L27/108

Abstract: Electronic data memory device for a high read current The invention provides a memory device arranged on a substrate ( 401 ) and having at least one memory cell ( 100 ) The memory cell comprises a storage capacitor ( 200 ) for storing an electrical charge and a selection transistor ( 300 ) for selecting the memory cell ( 100 ). The selection transistor comprises a first conduction electrode ( 301 ), a second conduction electrode ( 302 ) and a control electrode ( 303 ) , the control electrode ( 303 ) being provided by a gate unit ( 400 ) having a fin ( 405 ) projecting from the substrate ( 401 ), which fin is surrounded by a gate oxide layer ( 406 ) and a gate electrode layer ( 403 ) in such a way that first and second gate elements ( 408 a , 408 b) are provided at opposite lateral areas of the fin ( 405 ), a third gate element ( 408 c) being provided at an area of the fin ( 405 ) that is parallel to the surface of the substrate ( 401 ).