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公开(公告)号:DE10245249B4
公开(公告)日:2008-05-08
申请号:DE10245249
申请日:2002-09-27
Applicant: INFINEON TECHNOLOGIES AG
Inventor: HENNINGER RALF , HIRLER FRANZ
IPC: H01L21/336 , H01L21/225 , H01L29/417 , H01L29/423 , H01L29/45 , H01L29/78
Abstract: An insulating layer (4) projects over the spacer along the surface of the semiconductor region (9), serving as a dopant source for the semiconductor zone (11) and a channel zone in the semiconductor region (9) runs along the insulating layer (4). An Independent claim is included for the corresponding manufacture.
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公开(公告)号:DE102004005774A1
公开(公告)日:2005-08-25
申请号:DE102004005774
申请日:2004-02-05
Applicant: INFINEON TECHNOLOGIES AG
Inventor: HENNINGER RALF , HIRLER FRANZ , HILLER ULI , ROPOHL JAN
IPC: H01L21/336 , H01L29/06 , H01L29/40 , H01L29/423 , H01L29/45 , H01L29/74 , H01L29/78 , H01L31/111
Abstract: A method for fabrication of gate electrodes in a field-plate (magnetoresistive) trench transistor (1) having one, or more, trenches (3) and mesa zones (8), involves applying a gate electrode layer (7) on to the cell field so that the gate electrode layer (7) within or above the trenches (3) has indentations or pockets, and then applying a mask layer (10) on to the cell field. The mask layer (10) is etched-back so that only within the indentations or pockets of the gate electrode layer (7) does the residual masking layer remain, and the gate electrode layer (7) is etched-back using the residual mask layer (10) as the etching mask so that only within/above the trenches (5) does the residual gate electrode layer remain. An independent claim is given for a magneto resistive trench transistor.
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公开(公告)号:DE10339488B3
公开(公告)日:2005-04-14
申请号:DE10339488
申请日:2003-08-27
Applicant: INFINEON TECHNOLOGIES AG
Inventor: HIRLER FRANZ , DEBOY GERALD , HENNINGER RALF
IPC: H01L29/06 , H01L29/08 , H01L29/40 , H01L29/417 , H01L29/423 , H01L29/739 , H01L29/78 , H01L29/861 , H01L29/872
Abstract: The semiconductor component has a drift zone (40) formed below one surface (101) of a semiconductor body (100) so that it extends laterally between 2 doped terminal regions (20,30), at least one field electrode (50) projecting into the drift zone from the surface of the semiconductor body and electrically insulated from the semiconductor body by an insulation layer (52).
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公开(公告)号:DE10245249A1
公开(公告)日:2004-04-15
申请号:DE10245249
申请日:2002-09-27
Applicant: INFINEON TECHNOLOGIES AG
Inventor: HENNINGER RALF , HIRLER FRANZ
IPC: H01L21/225 , H01L21/336 , H01L29/417 , H01L29/423 , H01L29/45 , H01L29/78
Abstract: An insulating layer (4) projects over the spacer along the surface of the semiconductor region (9), serving as a dopant source for the semiconductor zone (11) and a channel zone in the semiconductor region (9) runs along the insulating layer (4). An Independent claim is included for the corresponding manufacture.
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公开(公告)号:DE10212149A1
公开(公告)日:2003-10-16
申请号:DE10212149
申请日:2002-03-19
Applicant: INFINEON TECHNOLOGIES AG
Inventor: HENNINGER RALF , HIRLER FRANZ , KRUMREY JOACHIM , RIEGER WALTER , POELZL MARTIN
IPC: H01L29/06 , H01L29/40 , H01L29/417 , H01L29/78 , H01L27/105
Abstract: The switching behavior of a transistor configuration is improved by providing a shielding electrode in an edge region. The shielding electrode surrounds at least sections of an active cell array. The capacitance between an edge gate structure and a drain zone and hence the gate-drain capacitance CGD of the transistor configuration is reduced by the shielding electrode located in the edge region.
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公开(公告)号:DE102004009602B4
公开(公告)日:2009-09-17
申请号:DE102004009602
申请日:2004-02-27
Applicant: INFINEON TECHNOLOGIES AG
Inventor: HENNINGER RALF , HIRLER FRANZ
IPC: H01L29/78 , H01L31/119
Abstract: A trench transistor has a cell array, in which at least one cell array trench ( 2 ) is provided, and an edge structure framing the cell array. An edge trench ( 15 ) spaced apart from the cell array trenches ( 2 ) is provided in the edge structure.
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公开(公告)号:DE10212144B4
公开(公告)日:2005-10-06
申请号:DE10212144
申请日:2002-03-19
Applicant: INFINEON TECHNOLOGIES AG
Inventor: KRUMREY JOACHIM , HIRLER FRANZ , HENNINGER RALF , POELZL MARTIN , RIEGER WALTER
IPC: H01L29/06 , H01L29/40 , H01L29/423 , H01L29/78
Abstract: The transistor structure has an array of IGBTs (Insulated Gate Bipolar Transistors) side-by-side accommodated in trenches (9). The trenches are connected at one end to a cross-trench (91). There is a gate structure (201), first and second portions (212,202), a source zone and a drain zone. There are metalized areas (20,21) with through contacts (31,32), touching the gate and source structures respectively.
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公开(公告)号:DE10258467B3
公开(公告)日:2004-09-30
申请号:DE10258467
申请日:2002-12-13
Applicant: INFINEON TECHNOLOGIES AG
Inventor: HENNINGER RALF , HIRLER FRANZ , ZUNDEL MARKUS , PFIRSCH FRANK
IPC: H01L21/265 , H01L21/329 , H01L21/336 , H01L21/337 , H01L29/06 , H01L29/10 , H01L29/40 , H01L29/423 , H01L29/78 , H01L29/808 , H01L29/872 , H01L29/861
Abstract: Power semiconductor component comprises semiconductor body (1,2) having trenches (4,5) with sidewalls inserted from upper surface of body, drift zone formed in regions bordering trenches, and field electrode (15). Field electrode is formed in lower region of trenches away from upper surface of body. Compensation regions of conducting type opposite that of drift zone are formed parallel to trench side walls in region bordering trenches. An independent claim is also included for a process for the production of the power semiconductor component.
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公开(公告)号:DE10212144A1
公开(公告)日:2003-10-30
申请号:DE10212144
申请日:2002-03-19
Applicant: INFINEON TECHNOLOGIES AG
Inventor: KRUMREY JOACHIM , HIRLER FRANZ , HENNINGER RALF , POELZL MARTIN , RIEGER WALTER
IPC: H01L29/06 , H01L29/40 , H01L29/423 , H01L29/78
Abstract: The transistor structure has an array of IGBTs (Insulated Gate Bipolar Transistors) side-by-side accommodated in trenches (9). The trenches are connected at one end to a cross-trench (91). There is a gate structure (201), first and second portions (212,202), a source zone and a drain zone. There are metalized areas (20,21) with through contacts (31,32), touching the gate and source structures respectively.
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公开(公告)号:DE102004005774B4
公开(公告)日:2006-09-28
申请号:DE102004005774
申请日:2004-02-05
Applicant: INFINEON TECHNOLOGIES AG
Inventor: HENNINGER RALF , HIRLER FRANZ , HILLER ULI , ROPOHL JAN
IPC: H01L21/336 , H01L29/06 , H01L29/40 , H01L29/423 , H01L29/45 , H01L29/74 , H01L29/78 , H01L31/111
Abstract: A method for fabrication of gate electrodes in a field-plate (magnetoresistive) trench transistor (1) having one, or more, trenches (3) and mesa zones (8), involves applying a gate electrode layer (7) on to the cell field so that the gate electrode layer (7) within or above the trenches (3) has indentations or pockets, and then applying a mask layer (10) on to the cell field. The mask layer (10) is etched-back so that only within the indentations or pockets of the gate electrode layer (7) does the residual masking layer remain, and the gate electrode layer (7) is etched-back using the residual mask layer (10) as the etching mask so that only within/above the trenches (5) does the residual gate electrode layer remain. An independent claim is given for a magneto resistive trench transistor.
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