Abstract:
PROBLEM TO BE SOLVED: To provide a method for manufacturing a non-volatile semiconductor memory cell (SZ) having a separate tunnel window cell (TF). SOLUTION: The method includes the step for forming the window cell (TF) having a tunnel zone (TG), a tunnel layer (4), a tunnel window memory layer (T5), a dielectric tunnel window layer (T6), and a tunnel window control electrode layer (T7), and the step for forming a transistor memory cell (TZ) having a channel zone (KG), a gate layer (3), a memory layer (5), a dielectric layer (6), and a control electrode layer (7). By the manufacturing method, the tunnel zone (TG) is formed in a late implantation step by tunnel implantation (I T ) using the window cell (TF) as a mask. The resulting memory cell has a small area requirement and a high number of program/clear cycles. COPYRIGHT: (C)2007,JPO&INPIT
Abstract:
The device has electronic chips and a memory device with a stored classification map with position and classification information for at least one part of the chip. The position information gives the position of each chip on the wafer and the classification information gives a classification of each chip in accordance with a given criterion. An Independent claim is also included for a wafer manufacturing method.
Abstract:
A non-volatile semiconductor storage cell comprises an active region (AA) formed by insulating regions (STI) in a semiconductor substrate (1); and a succession of layers comprising a storage layer (FG), a dielectric layer (DS) and a control layer (CG) formed on the surface of the substrate. At least one part of the overlapping regions of the active region and the succession of layers forms a tunnel window region with a tunnel layer (TS). The active region has a sharp edge (K) on the surface of the tunnel layer in the tunnel window region. An Independent claim is also included for the production of the non-volatile semiconductor storage cell. Preferred Features: The sharp edge is formed on a transition to the insulating region. The insulating regions have flat trench insulations.
Abstract:
The invention relates to a non-volatile semiconductor memory location comprising a semiconductor substrate (1), a first insulating layer (3), a charge-storing layer (4), a second insulating layer (5), and a control layer (6). The invention also relates to a corresponding production method according to which, in order to improve the temperature properties, the charge-storing layer (4) is constructed by a dielectric having a low energy gap.
Abstract:
A method for producing a non-volatile semiconductor memory cell with a separate tunnel window cell includes the step of forming a tunnel zone in a late implantation step by performing a tunnel implantation with the aid of a tunnel window cell as a mask. The resulting memory cell has a small area requirement and a high number of program/clear cycles.