2.
    发明专利
    未知

    公开(公告)号:DE10154981A1

    公开(公告)日:2003-05-15

    申请号:DE10154981

    申请日:2001-10-31

    Abstract: A mark configuration for the alignment and/or determination of a relative position of at least two planes in relation to one another in a substrate and/or in layers on a substrate during lithographic exposure, in particular, in the case of a wafer during the production of DRAMs, includes a mark structure, and at least one layer of a definable thickness underneath the mark structure for adjusting the physical position of the mark structure relative to a reference plane in or on the substrate. Also provided is a wafer having such a configuration and a process for providing such a configuration. The invention allows a mark configuration to have mark structures exhibiting good contrast regardless of the design or the process conditions.

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