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公开(公告)号：WO03061004A2
公开(公告)日：2003-07-24
申请号：PCT/DE0300080
申请日：2003-01-13
Applicant: INFINEON TECHNOLOGIES AG , BREDERLOW RALF , ELBE ASTRID , KREUPL FRANZ , LUYKEN JOHANNES , NEUHAUSER ROBERT , PAULUS CHRISTIAN , SCHEPERS JOERG , THEWES ROLAND
Inventor： BREDERLOW RALF , ELBE ASTRID , KREUPL FRANZ , LUYKEN JOHANNES , NEUHAUSER ROBERT , PAULUS CHRISTIAN , SCHEPERS JOERG , THEWES ROLAND
IPC: G06K19/073 , H01L23/58 , H01L23/544
CPC classification number: B82Y10/00 , G06K19/073 , G06K19/07372 , H01L23/576 , H01L2223/5444 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
Abstract: According to the invention, an electrical characteristic of a material layer (3) or layer-type material structure is measured at various points provided with connection contacts (5, 6). A mean value of the measurement, taken from a base set of IC chips, is subtracted from a respective value, and a digital word for identifying the chip in question is formed on the basis of the result thus obtained, for each IC chip. The measurement can be carried out by means of a cross-correlation, the measuring regions crossing over each other.
Abstract translation: 一材料层（3）或所述材料的层状结构的电特性在不同的位置进行测定，与所述连接接点（5,6）被提供。 采取大约IC芯片平均测量的群的部分中的相应值的是由和由这样获得的结果，以每个IC芯片，一个数字字为各个芯片的识别中减去。 所述测量可以用互相关，其中，所述测量范围被交叉地设置制成。
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公开(公告)号：DE102005027713A1
公开(公告)日：2006-12-21
申请号：DE102005027713
申请日：2005-06-15
Applicant: INFINEON TECHNOLOGIES AG
Inventor： HOFMANN FRANZ , LUYKEN JOHANNES , SPECHT MICHAEL
IPC: H01L27/115 , H01L21/8247
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公开(公告)号：DE10201645A1
公开(公告)日：2003-08-07
申请号：DE10201645
申请日：2002-01-17
Applicant: INFINEON TECHNOLOGIES AG
Inventor： BREDERLOW RALF , ELBE ASTRID , KREUPL FRANZ , LUYKEN JOHANNES , NEUHAUSER ROBERT , PAULUS CHRISTIAN , SCHEPERS JOERG , THEWES ROLAND
IPC: G06K19/073 , H01L23/58 , G01R31/28
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公开(公告)号：DE102006003392A1
公开(公告)日：2007-05-03
申请号：DE102006003392
申请日：2006-01-24
Applicant: INFINEON TECHNOLOGIES AG
Inventor： ROESNER WOLFGANG , SPECHT MICHAEL , HOFMANN FRANZ , LUYKEN JOHANNES
IPC: H01L27/115 , H01L21/8247
Abstract: Non-volatile memory cells comprises cells (5) formed on a projection (10) of a semiconductor wafer. A transistor is formed having regions (30,32) with two connections (30,32) each comprising connecting regions (26,26') and charging layers (20,20') on an upper surface (12). A third region (34) has a gate electrode and a non-conductive gate layer (36) at least partly on the projection sidewalls with the gate electrode contacting both charging layers. An independent claim is also included for production processes for the above.
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公开(公告)号：DE10123364A1
公开(公告)日：2002-11-28
申请号：DE10123364
申请日：2001-05-14
Applicant: INFINEON TECHNOLOGIES AG
Inventor： LUYKEN JOHANNES , HOFMANN FRANZ , ROESNER WOLFGANG , HARTWICH JESSICA
Abstract: An electronic device has a functional element coupled electrically with at least a first and a second terminal and a maintenance voltage supply coupled electrically with at least the first or second terminal. In an electronic device has a functional element coupled electrically with at least a first and a second terminal for supplying the maintenance voltage for operation, and a maintenance voltage supply coupled electrically with at least the first or second terminal, the maintenance voltage supply is a molecular photodiode of a first molecular material (I). An Independent claim is also included for integrated circuits with several electrically coupled devices of this type.
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Patent Agency Ranking
公开(公告)号：DE102005039351A1
公开(公告)日：2007-02-01
申请号：DE102005039351
申请日：2005-08-19
Applicant: INFINEON TECHNOLOGIES AG
Inventor： HOFMANN FRANZ , LUYKEN JOHANNES , SPECHT MICHAEL
IPC: H01L21/8247 , H01L27/115
Abstract: The invention relates to a method for fabricating stacked non-volatile memory cells. Further, the invention relates to stacked non-volatile memory cells. The invention particularly relates to the field of non-volatile NAND memories having non-volatile stacked memory cells. The stacked non-volatile memory cells are formed on a semiconductor wafer, having a bulk semi-conductive substrate and an SOI semi-conductive layer and are arranged as a bulk FinFET transistor and an SOI FinFet transistor being arranged on top of the bulk FinFET transistor. Both the FinFET transistor and the SOI FinFet transistor are attached to a common charge-trapping layer. A word line with sidewalls is arranged on top of said patterned charge-trapping layer and a spacer oxide layer is arranged on the sidewalls of said word line.
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公开(公告)号：DE10255599A1
公开(公告)日：2004-04-22
申请号：DE10255599
申请日：2002-11-28
Applicant: INFINEON TECHNOLOGIES AG
Inventor： LUYKEN JOHANNES , HANEDER THOMAS , HOFMANN FRANZ , FRITZ MICHAELA , HANKE HANS-CHRISTIAN , DERTINGER STEPHAN , MARTIN ALFRED , LEHMANN VOLKER
IPC: H01L31/102
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公开(公告)号：DE10204875C1
公开(公告)日：2003-02-27
申请号：DE10204875
申请日：2002-02-06
Applicant: INFINEON TECHNOLOGIES AG
Inventor： LUYKEN JOHANNES , HOFMANN FRANZ , SIPRAK DOMAGOJ , BREDERLOW RALF , KREUPL FRANZ , PAULUS CHRISTIAN , THEWES ROLAND , WEBER WERNER , ELBE ASTRID , NEUHAUSER ROBERT , SCHEPERS JOERG
IPC: G06K19/073 , H01L23/58 , G06F12/14 , H01L51/10
Abstract: The IC chip has a layer structure with given electrical characteristics and a circuit stage for checking the latter electrical characteristics. The layer structure is provided by a resistance layer and 2 associated electrodes, the resistance layer provided as a molecular layer with an electrical resistance which can be switched both locally and globally between different conduction states. An Independent claim for a protection method for an IC chip is also included.
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公开(公告)号：DE10201645B4
公开(公告)日：2007-04-26
申请号：DE10201645
申请日：2002-01-17
Applicant: INFINEON TECHNOLOGIES AG
Inventor： BREDERLOW RALF , ELBE ASTRID , KREUPL FRANZ , LUYKEN JOHANNES , NEUHAUSER ROBERT , PAULUS CHRISTIAN , SCHEPERS JOERG , THEWES ROLAND
IPC: G01R31/28 , G06K19/073 , H01L23/58
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公开(公告)号：DE102005027713B4
公开(公告)日：2007-03-29
申请号：DE102005027713
申请日：2005-06-15
Applicant: INFINEON TECHNOLOGIES AG
Inventor： HOFMANN FRANZ , LUYKEN JOHANNES , SPECHT MICHAEL
IPC: H01L27/115 , H01L21/8247
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