公开(公告)号：WO0117019A3

公开(公告)日：2001-05-10

申请号：PCT/DE0002866

申请日：2000-08-23

Applicant: INFINEON TECHNOLOGIES AG ,  TEMMLER DIETMAR ,  BENZINGER HERBERT ,  KARCHER WOLFRAM ,  PUSCH CATHARINA ,  SCHREMS MARTIN ,  FAUL JUERGEN

Inventor： TEMMLER DIETMAR ,  BENZINGER HERBERT ,  KARCHER WOLFRAM ,  PUSCH CATHARINA ,  SCHREMS MARTIN ,  FAUL JUERGEN

IPC: H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/10861 ,  H01L27/10832

Abstract: The invention comprises a memory with a storage cell (100) that is formed in a substrate (105) and consists of a trench capacitor (110) and a transistor (160). The trench capacitor (110) is connected to the transistor (160) with a self-aligned connection (220). The transistor (160) at least partially covers said trench capacitor (110). The trench capacitor (110) is filled with a conductive trench filling and an insulating cover layer (135) is located on said conductive trench filling (130). An epitaxy layer (245) is located above said insulating cover layer (135). The transistor (160) is formed in said epitaxy layer (245). The self-aligned connection (220) is formed in a contact trench (205) and consists of an insulation collar (235) into which a conductive material (225) is introduced. A conductive cap (230) is formed on said conductive material.

Abstract translation: 本发明包括具有存储单元（100）的存储器，存储单元（100）形成在衬底（105）中并由沟槽电容器（110）和晶体管（160）组成。 沟槽电容器（110）通过自对准端子（220）连接到晶体管（160）。 晶体管（160）至少部分地覆盖沟槽电容器（110）。 沟槽电容器（110）填充有导电沟槽填充物（130），并且在导电沟槽填充物（130）上是绝缘覆盖层（135）。 绝缘覆盖层（135）之上是外延层（245）。 晶体管（160）形成在外延层（245）中。 自对准端子（220）形成在接触沟槽（205）中并且由其中引入导电材料（225）的绝缘轴环（235）组成。 在导电材料上形成导电帽（230）。

公开(公告)号：DE19941148A1

公开(公告)日：2001-04-19

申请号：DE19941148

申请日：1999-08-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： TEMMLER DIETMAR ,  BENZINGER HERBERT ,  KARCHER WOLFRAM ,  PUSCH CATHARINA ,  SCHREMS MARTIN ,  FAUL JUERGEN

IPC: H01L21/8242 ,  H01L27/108

Abstract: A memory having a memory cell formed in a substrate and including a trench capacitor and a transistor and a method for producing the memory includes connecting the trench capacitor to the transistor with a self-aligned connection. The transistor at least partly covers the trench capacitor. The trench capacitor is filled with a conductive trench filling and an insulating covering layer is situated on the conductive trench filling. An epitaxial layer is situated above the insulating covering layer. The transistor is formed in the epitaxial layer. The self-aligned connection is formed in a contact trench and includes an insulation collar in which a conductive material is introduced. A conductive cap is formed on the conductive material.

公开(公告)号：DE10063991B4

公开(公告)日：2005-06-02

申请号：DE10063991

申请日：2000-12-21

Applicant: INFINEON TECHNOLOGIES AG

Inventor： PUSCH CATHARINA ,  WITTMANN REINHARD ,  FRANOSCH MARTIN

IPC: B81B3/00 ,  B81C1/00

Abstract: A method for the manufacture of micro-mechanical components from a stack of layers having at least a substrate, a sacrificial layer and a layer which is to be undercut includes forming at least one etch hole in the layer, which is to be undercut, and providing at least one passivation layer for controlling a selective depositing of a cover material which closes each of the etch holes after a step of etching the sacrificial layer. The passivation layer makes it possible that the undercut layer elements do not become excessively thick or grow together with the substrate due to the deposition of the cover material.

公开(公告)号：DE10063991A1

公开(公告)日：2002-07-04

申请号：DE10063991

申请日：2000-12-21

Applicant: INFINEON TECHNOLOGIES AG

Inventor： PUSCH CATHARINA ,  WITTMANN REINHARD ,  FRANOSCH MARTIN

IPC: B81B3/00 ,  B81C1/00

Abstract: A method for the manufacture of micro-mechanical components from a stack of layers having at least a substrate, a sacrificial layer and a layer which is to be undercut includes forming at least one etch hole in the layer, which is to be undercut, and providing at least one passivation layer for controlling a selective depositing of a cover material which closes each of the etch holes after a step of etching the sacrificial layer. The passivation layer makes it possible that the undercut layer elements do not become excessively thick or grow together with the substrate due to the deposition of the cover material.

公开(公告)号：DE19941147A1

公开(公告)日：2001-03-22

申请号：DE19941147

申请日：1999-08-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： TEMMLER DIETMAR ,  BENZINGER HERBERT ,  KARCHER WOLFRAM ,  PUSCH CATHARINA ,  SCHREMS MARTIN ,  FAUL JUERGEN

IPC: H01L21/20 ,  H01L21/8242 ,  H01L27/108

Abstract: Production of an epitaxial layer comprises: preparing substrate (105) having a single crystalline region (107) and an electrically insulated region (108); growing epitaxial layer (245) on the single crystalline region; and partially removing the epitaxial layer. Production of an epitaxial layer comprises: preparing substrate (105) having a single crystalline region (107) and an electrically insulated region (108); growing epitaxial layer (245) on the single crystalline region, in which the electrically insulated region is partially grown laterally by the epitaxial layer and forms an epitaxial closing joint (275); and partially removing the epitaxial layer above the electrically insulated region so that the epitaxial closing joint is partially removed. Preferred Features: The epitaxial layer is removed by anisotropic etching. The single crystalline region consists of silicon and the electrically insulated region consists of silicon oxide.

公开(公告)号：DE19941148B4

公开(公告)日：2006-08-10

申请号：DE19941148

申请日：1999-08-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： TEMMLER DIETMAR ,  BENZINGER HERBERT ,  KARCHER WOLFRAM ,  PUSCH CATHARINA ,  SCHREMS MARTIN ,  FAUL JUERGEN

IPC: H01L27/108 ,  H01L21/8242

Abstract: A memory having a memory cell formed in a substrate and including a trench capacitor and a transistor and a method for producing the memory includes connecting the trench capacitor to the transistor with a self-aligned connection. The transistor at least partly covers the trench capacitor. The trench capacitor is filled with a conductive trench filling and an insulating covering layer is situated on the conductive trench filling. An epitaxial layer is situated above the insulating covering layer. The transistor is formed in the epitaxial layer. The self-aligned connection is formed in a contact trench and includes an insulation collar in which a conductive material is introduced. A conductive cap is formed on the conductive material.

公开(公告)号：DE59802570D1

公开(公告)日：2002-01-31

申请号：DE59802570

申请日：1998-09-25

Applicant: INFINEON TECHNOLOGIES AG

Inventor： PUSCH CATHARINA ,  SCHNEIDER GERMAR

IPC: C09G1/02 ,  C09K3/14 ,  H01L21/304 ,  H01L21/306 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/463

Abstract: The invention relates to a polishing agent characterised in that it is comprised of a solution containing fluoride and that polishing grains are suspended in said solution. The polishing grains are made of a chemically resistant material. The invention also relates to the use of said polishing agent in the planishing of semiconductor substrates or substrates made of 3d transition elements, silicides, refractory metals, metal oxides or oxidic supraconductors.