公开(公告)号：WO0117019A3

公开(公告)日：2001-05-10

申请号：PCT/DE0002866

申请日：2000-08-23

Applicant: INFINEON TECHNOLOGIES AG ,  TEMMLER DIETMAR ,  BENZINGER HERBERT ,  KARCHER WOLFRAM ,  PUSCH CATHARINA ,  SCHREMS MARTIN ,  FAUL JUERGEN

Inventor： TEMMLER DIETMAR ,  BENZINGER HERBERT ,  KARCHER WOLFRAM ,  PUSCH CATHARINA ,  SCHREMS MARTIN ,  FAUL JUERGEN

IPC: H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/10861 ,  H01L27/10832

Abstract: The invention comprises a memory with a storage cell (100) that is formed in a substrate (105) and consists of a trench capacitor (110) and a transistor (160). The trench capacitor (110) is connected to the transistor (160) with a self-aligned connection (220). The transistor (160) at least partially covers said trench capacitor (110). The trench capacitor (110) is filled with a conductive trench filling and an insulating cover layer (135) is located on said conductive trench filling (130). An epitaxy layer (245) is located above said insulating cover layer (135). The transistor (160) is formed in said epitaxy layer (245). The self-aligned connection (220) is formed in a contact trench (205) and consists of an insulation collar (235) into which a conductive material (225) is introduced. A conductive cap (230) is formed on said conductive material.

Abstract translation: 本发明包括具有存储单元（100）的存储器，存储单元（100）形成在衬底（105）中并由沟槽电容器（110）和晶体管（160）组成。 沟槽电容器（110）通过自对准端子（220）连接到晶体管（160）。 晶体管（160）至少部分地覆盖沟槽电容器（110）。 沟槽电容器（110）填充有导电沟槽填充物（130），并且在导电沟槽填充物（130）上是绝缘覆盖层（135）。 绝缘覆盖层（135）之上是外延层（245）。 晶体管（160）形成在外延层（245）中。 自对准端子（220）形成在接触沟槽（205）中并且由其中引入导电材料（225）的绝缘轴环（235）组成。 在导电材料上形成导电帽（230）。

公开(公告)号：WO0237557A3

公开(公告)日：2002-08-01

申请号：PCT/EP0111076

申请日：2001-09-25

Applicant: INFINEON TECHNOLOGIES AG ,  KARCHER WOLFRAM ,  LEHR MATTHIAS ,  ZEILER DIETER

Inventor： KARCHER WOLFRAM ,  LEHR MATTHIAS ,  ZEILER DIETER

IPC: H01L21/02 ,  H01L21/311 ,  H01L21/768 ,  H01L23/522 ,  H01L21/3205

CPC classification number: H01L28/40 ,  H01L21/31116 ,  H01L21/31122 ,  H01L21/76838 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The invention relates to a method for producing an integrated circuit, comprising the following steps: a circuit substrate (1) is prepared; a first metallising area (10a) and a second metallising area (10b) consisting of a first metal are provided in the circuit substrate (1); an intermediate layer (15) is provided over the first metallising area (10a) and the second metallising area (10b); the intermediate layer (15) over the first metallising area (10a) is removed by etching, an oxide film (100) being simultaneously formed on the surface of the first metallising area (10a); and the oxide film (100) on the surface of the first metallising area (10a) is at least partially transformed so that a conductive compound is created from the first metal, by means of the oxide film (100), forming a connection to the first metallising area (10a) on the surface of the resulting structure.

Abstract translation: 本发明提供了一种集成电路制造方法，包括以下步骤：提供电路衬底（1）; 在所述电路基板（1）中提供第一金属化区域（10a）和第二金属化区域（10b）; 在第一金属化区域（10a）和第二金属化区域（10b）上提供中间层（15）; 通过蚀刻工艺在第一金属化区域（10a）上去除中间层（15），同时在第一金属化区域（10a）的表面上形成氧化物膜（100）; 和第一金属化（10A）的表面上至少部分地将所述氧化膜（100），从而通过氧化膜（100）中的第一金属的导电连接形成，其具有将所得的表面上的第一金属化（10A）的连接 结构形式。

公开(公告)号：DE19941148A1

公开(公告)日：2001-04-19

申请号：DE19941148

申请日：1999-08-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： TEMMLER DIETMAR ,  BENZINGER HERBERT ,  KARCHER WOLFRAM ,  PUSCH CATHARINA ,  SCHREMS MARTIN ,  FAUL JUERGEN

IPC: H01L21/8242 ,  H01L27/108

Abstract: A memory having a memory cell formed in a substrate and including a trench capacitor and a transistor and a method for producing the memory includes connecting the trench capacitor to the transistor with a self-aligned connection. The transistor at least partly covers the trench capacitor. The trench capacitor is filled with a conductive trench filling and an insulating covering layer is situated on the conductive trench filling. An epitaxial layer is situated above the insulating covering layer. The transistor is formed in the epitaxial layer. The self-aligned connection is formed in a contact trench and includes an insulation collar in which a conductive material is introduced. A conductive cap is formed on the conductive material.

公开(公告)号：DE19947053C1

公开(公告)日：2001-05-23

申请号：DE19947053

申请日：1999-09-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHREMS MARTIN ,  DRESCHER DIRK ,  WURZER HELMUT ,  KARCHER WOLFRAM

IPC: H01L21/8242 ,  H01L27/108

Abstract: Trench capacitor comprises: trench (108) having an upper region (109) and a lower region (111) formed in substrate (101); insulating collar (168) formed in upper region of trench; trenched sink (170) formed in the substrate and partially penetrating lower region of trench; a dielectric layer (164) made of tungsten oxide as capacitor dielectric; and a conducting trench filling (161) in the trench. An Independent claim is also included for a process for the production of the trench capacitor. Preferred Features: The conducting trench filling is made of a tungsten-containing material. A barrier layer made of silicon oxide, oxynitride, tungsten nitride, titanium nitride or tantalum nitride is arranged between the dielectric layer and the substrate.

公开(公告)号：DE102013221165A1

公开(公告)日：2014-04-24

申请号：DE102013221165

申请日：2013-10-18

Applicant: INFINEON TECHNOLOGIES AG

Inventor： FISCHER MARKUS ,  KARCHER WOLFRAM ,  JEANSANNETAS BARBARA

IPC: C23C14/34

Abstract: Eine Trägerplatte für ein Sputtertarget enthält ein Targetaufnahmeteil zum Aufnehmen eines zu sputternden Targets und eine Struktur zum Exponieren des Targetaufnahmeteils durch die Trägerplatte.

公开(公告)号：DE10010821A1

公开(公告)日：2001-09-13

申请号：DE10010821

申请日：2000-02-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： RUF ALEXANDER ,  KEGEL WILHELM ,  KARCHER WOLFRAM ,  SCHREMS MARTIN

IPC: H01L21/02 ,  H01L21/316 ,  H01L21/334 ,  H01L21/8242 ,  H01L27/108

Abstract: Increasing the capacity in a storage trench comprises depositing a first silicon oxide layer (4) in the trench; depositing a silicon layer (5) over the first layer to sufficiently cover the wall of the trench; and depositing a layer (6) containing an oxidizable metal. The silicon layer and the oxidizable metal layer are oxidized to form a layer containing a metal oxide and silicon oxide. An independent claim is also included for a trench capacitor comprising an inner wall covered with a silicon oxide layer which is covered with a metal oxide layer followed by a further silicon oxide layer. The remainder of the trench is filled with silicon. Preferred Features: Deposition is carried out by CVD or atomic layer deposition. The oxidizable metal is Ti, TiN, W, WN, Ta, TaN, WSi, TiSi or TaSi. Oxidation is carried out in an oxygen-containing atmosphere.

公开(公告)号：DE19941147A1

公开(公告)日：2001-03-22

申请号：DE19941147

申请日：1999-08-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： TEMMLER DIETMAR ,  BENZINGER HERBERT ,  KARCHER WOLFRAM ,  PUSCH CATHARINA ,  SCHREMS MARTIN ,  FAUL JUERGEN

IPC: H01L21/20 ,  H01L21/8242 ,  H01L27/108

Abstract: Production of an epitaxial layer comprises: preparing substrate (105) having a single crystalline region (107) and an electrically insulated region (108); growing epitaxial layer (245) on the single crystalline region; and partially removing the epitaxial layer. Production of an epitaxial layer comprises: preparing substrate (105) having a single crystalline region (107) and an electrically insulated region (108); growing epitaxial layer (245) on the single crystalline region, in which the electrically insulated region is partially grown laterally by the epitaxial layer and forms an epitaxial closing joint (275); and partially removing the epitaxial layer above the electrically insulated region so that the epitaxial closing joint is partially removed. Preferred Features: The epitaxial layer is removed by anisotropic etching. The single crystalline region consists of silicon and the electrically insulated region consists of silicon oxide.

公开(公告)号：DE19941148B4

公开(公告)日：2006-08-10

申请号：DE19941148

申请日：1999-08-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： TEMMLER DIETMAR ,  BENZINGER HERBERT ,  KARCHER WOLFRAM ,  PUSCH CATHARINA ,  SCHREMS MARTIN ,  FAUL JUERGEN

IPC: H01L27/108 ,  H01L21/8242

Abstract: A memory having a memory cell formed in a substrate and including a trench capacitor and a transistor and a method for producing the memory includes connecting the trench capacitor to the transistor with a self-aligned connection. The transistor at least partly covers the trench capacitor. The trench capacitor is filled with a conductive trench filling and an insulating covering layer is situated on the conductive trench filling. An epitaxial layer is situated above the insulating covering layer. The transistor is formed in the epitaxial layer. The self-aligned connection is formed in a contact trench and includes an insulation collar in which a conductive material is introduced. A conductive cap is formed on the conductive material.

公开(公告)号：DE59804614D1

公开(公告)日：2002-08-08

申请号：DE59804614

申请日：1998-01-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KARCHER WOLFRAM ,  LABS LUTZ

IPC: C23C16/02 ,  C23C16/42 ,  C23C16/44 ,  C23C16/455 ,  H01L21/205 ,  H01L21/28 ,  H01L21/285 ,  H01L21/768

Abstract: In a process for layer production on a surface by reacting gases together at the preheated surface, a protective gas is supplied to the surface before and/or during preheating. The protective gas is preferably a silane, especially SiH4 supplied together with a carrier gas (especially Ar), and the reactive gases consist of a metal halide together with a silane or H2.

公开(公告)号：DE10054936C1

公开(公告)日：2002-04-25

申请号：DE10054936

申请日：2000-11-06

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KARCHER WOLFRAM ,  ZEILER DIETER ,  LEHR MATTHIAS

IPC: H01L21/02 ,  H01L21/311 ,  H01L21/768 ,  H01L23/522

Abstract: Production of an integrated circuit comprises preparing a circuit substrate (1); providing a first metallizing region (10a) and a second metallizing region (10b) from a first metal in the substrate; providing an intermediate layer (15') over the metallizing regions; removing the intermediate layer by etching to form an oxide film (100') above the first metallizing region; and partially converting the oxide film to produce a conducting connection of a first metal and form a connection to the first metallizing region on the surface of the resulting structure. Conversion of the oxide film is carried out using CVD with a gas containing the first metal and a halogen. Preferred Features: The intermediate layer is structured so that it forms a connection to the second metallizing region on the surface of the resulting structure. The first metal is tungsten and the gas is WF6.