公开(公告)号：WO02086967A3

公开(公告)日：2003-09-25

申请号：PCT/EP0204308

申请日：2002-04-18

Applicant: INFINEON TECHNOLOGIES AG ,  STAUB RALF ,  AMON JUERGEN ,  URBANSKY NORBERT

Inventor： STAUB RALF ,  AMON JUERGEN ,  URBANSKY NORBERT

IPC: H01L21/28 ,  H01L21/285 ,  H01L21/3205 ,  H01L21/60 ,  H01L21/768 ,  H01L21/8242 ,  H01L23/52 ,  H01L27/108 ,  H01L21/283

CPC classification number: H01L21/76808 ,  H01L21/28512 ,  H01L21/76807 ,  H01L21/76877 ,  H01L21/76897 ,  H01L27/10829 ,  H01L27/10885 ,  H01L27/10888 ,  H01L27/10894 ,  Y10S257/905

Abstract: According to the invention, a contact hole is filled with a metal or a metal alloy when a bit line is brought into contact with a selection transistor of a dynamic memory unit on a semiconductor wafer. The semiconductor substrate in the contact hole comprises a dopant, and a liner layer is integrated between the semiconductor substrate and the metal filling.

Abstract translation: 根据本发明，配备有动态存储器单元的半导体晶片上的选择晶体管设置填充有金属或在与位线相接触的金属合金的接触孔，所述接触孔的半导体基板的掺杂和引入的半导体基板和金属填充物之间的衬垫层 是。

公开(公告)号：WO03007355A3

公开(公告)日：2003-09-18

申请号：PCT/EP0207507

申请日：2002-07-05

Applicant: INFINEON TECHNOLOGIES AG ,  KROENKE MATTHIAS ,  STAUB RALF ,  WANG KAE-HORNG

Inventor： KROENKE MATTHIAS ,  STAUB RALF ,  WANG KAE-HORNG

IPC: H01L21/60 ,  H01L21/768 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/28

CPC classification number: H01L27/10888 ,  H01L21/76895 ,  H01L21/76897 ,  H01L27/10829

Abstract: The invention relates to the production of one (or several) contacts on one or several active areas of a semiconductor disk, whereby one or several insulated control lines can be arranged on the active areas to be contacted. The control lines can, for example, be gate lines. The semiconductor element is produced in the following manner: a polysilicon layer is deposited on the semiconductor disk, the polysilicon layer is structured in order to produce a polysilicon contact over the active area, whereby the polysilicon contact covers the two control lines in an at least partial manner, a first insulator layer is applied to the semiconductor disk incorporating said polysilicon contact, the first insulator layer is partially removed to reveal the covering surface of the polysilicon contact and a metal layer is applied to the semiconductor disk for the electrical contacting of the polysilicon contact.

Abstract translation: 有在半导体晶片的一个或多个有源区，其中一个或多个分离的控制线可以被布置在有源区域的一个（或更多个）触点被接触生成。 控制线可以是，例如，到栅极线。 的半导体器件如下制造：在多晶硅接触的嵌入在半导体晶片上沉积多晶硅层，图案化多晶硅层以形成在所述有源区中的多晶硅接触，其中，所述多晶硅接触至少覆盖两条控制线部分，在半导体晶片上施加第一绝缘层 ，部分去除所述第一绝缘层以暴露该多晶硅接触的顶部表面和该半导体晶片上施加金属层用于使多晶硅接触的电接触。

公开(公告)号：WO0239488A3

公开(公告)日：2002-07-18

申请号：PCT/EP0110783

申请日：2001-09-18

Applicant: INFINEON TECHNOLOGIES AG ,  HILLIGER ANDREAS ,  STAUB RALF ,  LUEKEN EIKE

Inventor： HILLIGER ANDREAS ,  STAUB RALF ,  LUEKEN EIKE

IPC: H01L21/768 ,  H01L21/60 ,  H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/10885 ,  H01L21/76897

Abstract: The invention relates to a method for producing an integrated circuit comprising the following steps: preparing a semi-conductor substrate (1) with a contacting circuit area (SS); providing an insulating layer (IS) on the surface of the semi-conductor substrate (1); providing a contact hole (KL) in the insulating layer (IS) for making contacting the circuit area (SS); providing an insulating spacer area (10`) in at least the area above the contact hole (KL); providing at least three trenches (BG1; BG2; BG3), the first (BG1) of which is arranged next to the contact hole (KL), a second (BG2) is disposed across the contact hole (KL) and a third (BG3) is next to the contact hole (KL). The spacer area (10`) is placed between the first and the second trench (BG1; BG2) and the second and the third trench (BG2; BG3); filling the trenches (BG1; BG2; BG3) with a conductive material; and chemical-mechanical polishing of conductive material for producing three separated trenches (BL1; BL2; BL3).

Abstract translation: 本发明提供了一种集成电路制造方法，包括以下步骤：提供具有要接触的电路区域（SS）的半导体衬底（1） 在半导体衬底（1）的表面上提供绝缘层（IS）; 在绝缘层（IS）中提供用于接触电路区域（SS）的接触孔（KL）; 至少在接触孔（KL）的上部区域中设置绝缘间隔物区域（10'）; 提供至少三个沟槽（BG1; BG2，BG3），其中，第一线沟槽（BG1）邻近于通过接触孔（KL）和第三线沟槽（BG3）相邻的接触孔的接触孔（KL），第二线沟槽（BG2）的 之间（KL），其中，所述间隔区（10“）的第一和第二线沟槽（BG1; BG2）之间是左和所述第二和第三线沟槽（BG3 BG2）; 用线材填充沟槽（BG1，BG2，BG3）; 并对导体材料进行化学机械抛光以产生三个单独的引线（BL1; BL2; BL3）。

公开(公告)号：DE10133873B4

公开(公告)日：2005-04-28

申请号：DE10133873

申请日：2001-07-12

Applicant: INFINEON TECHNOLOGIES AG

Inventor： WANG KAE-HORNG ,  STAUB RALF ,  KROENKE MATTHIAS

IPC: H01L21/60 ,  H01L21/768 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/283

Abstract: One (or more) contacts are produced on one or more active areas of a semiconductor wafer, it being possible for one or more isolated control lines to be arranged on the active areas with which contact is to be made. The control lines may, for example, be gate lines. The semiconductor component is fabricated in the following way: application of a polysilicon layer to the semiconductor wafer, patterning of the polysilicon layer, in order to produce a polysilicon contact above the active area, the polysilicon contact at least partly covering the two control lines, application of a first insulator layer to the semiconductor wafer, with the polysilicon contact being embedded, partial removal of the first insulator layer, so that at least the upper surface of the polysilicon contact is uncovered, and application of a metal layer to the semiconductor wafer in order to make electrical contact with the polysilicon contact.

公开(公告)号：DE10153200A1

公开(公告)日：2003-05-15

申请号：DE10153200

申请日：2001-10-27

Applicant: INFINEON TECHNOLOGIES AG

Inventor： AMON JUERGEN ,  FAUL JUERGEN ,  SCHUSTER THOMAS ,  STAUB RALF

IPC: H01L21/28 ,  H01L21/336 ,  H01L21/60 ,  H01L21/768 ,  H01L21/316

Abstract: Filling openings in a gate electrode layer on a semiconductor wafer comprises growing a gate oxide layer on the wafer; producing a gate electrode layer on the gate oxide layer; defining opening regions; etching the gate electrode layer up to the gate oxide layer in the opening regions; nitriding the gate oxide layer in the opening regions; and applying a BPSG layer to fill the opening regions. Preferred Features: After exposing the opening regions, an additional oxide layer is thermally produced which is nitrided in a further step. At least one opening region is a source/drain region, in which side wall spacers are exposed in the exposed source/drain region. A source/drain doping is formed in the wafer over the oxide layer in the exposed source/drain region.

公开(公告)号：DE10119873A1

公开(公告)日：2002-10-31

申请号：DE10119873

申请日：2001-04-24

Applicant: INFINEON TECHNOLOGIES AG

Inventor： STAUB RALF ,  AMON JUERGEN ,  URBANSKY NORBERT

IPC: H01L21/28 ,  H01L21/285 ,  H01L21/3205 ,  H01L21/60 ,  H01L21/768 ,  H01L21/8242 ,  H01L23/52 ,  H01L27/108 ,  H01L21/283

Abstract: According to the invention, a contact hole is filled with a metal or a metal alloy when a bit line is brought into contact with a selection transistor of a dynamic memory unit on a semiconductor wafer. The semiconductor substrate in the contact hole comprises a dopant, and a liner layer is integrated between the semiconductor substrate and the metal filling.

公开(公告)号：DE10153200B4

公开(公告)日：2005-08-04

申请号：DE10153200

申请日：2001-10-27

Applicant: INFINEON TECHNOLOGIES AG

Inventor： AMON JUERGEN ,  FAUL JUERGEN ,  SCHUSTER THOMAS ,  STAUB RALF

IPC: H01L21/28 ,  H01L21/336 ,  H01L21/60 ,  H01L21/768 ,  H01L21/316

公开(公告)号：DE10200428A1

公开(公告)日：2003-04-30

申请号：DE10200428

申请日：2002-01-09

Applicant: INFINEON TECHNOLOGIES AG

Inventor： STAUB RALF ,  HILLIGER ANDREAS

IPC: H01L21/768 ,  H01L21/28

Abstract: Production of contact structures in a metallizing on a semiconductor wafer comprises preparing a wafer (S) having an active region (B); applying a first insulating layer (11) on the wafer; applying a hard mask layer (H) on the insulating layer; forming a contact region on the mask layer in the region of the active region; opening the mask layer in the contact region; depositing a second insulating layer (12) on the structured mask layer; forming a metallizing region on the second insulating layer partially over the structured contact region; opening the second insulating region in the metallizing region; and depositing an electrically conducting layer to fill the trenches. Preferred Features: The hard mask layer is opened and/or the second insulating layer is opened using a photolithographic etching process. The hard mask layer is a nitride layer. The second insulating layer is a siliane oxide layer.

公开(公告)号：DE10055290C1

公开(公告)日：2002-07-25

申请号：DE10055290

申请日：2000-11-08

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HILLIGER ANDREAS ,  STAUB RALF ,  LUEKEN ELKE

IPC: H01L21/768 ,  H01L21/60 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/283

Abstract: The invention relates to a method for producing an integrated circuit comprising the following steps: preparing a semi-conductor substrate ( 1 ) with a contacting circuit area (SS); providing an insulating layer (IS) on the surface of the semi-conductor substrate ( 1 ): providing a contact hole (KL) in the insulating layer (IS) for making contacting the circuit area (SS); providing an insulating spacer area ( 10 ') in at least the area above the contact hole (KL); providing at least three trenches (BG 1 ; BG 2 ; BG 3 ), the first (BG 1 ) of which is arranged next to the contact hole (KL), a second (BG 2 ) is disposed across the contact hole (KL) and a third (BG 3 ) is next to the contact hole (KL). The spacer area ( 10 ') is placed between the first and the second trench (BG 1 ; BG 2 ) and the second and the third trench (BG 2 ; BG 3 ); filling the trenches (BG 1 ; BG 2 ; BG 3 ) with a conductive material; and chemical-mechanical polishing of conductive material for producing three separated trenches (BL 1 ; BL 2 ; BL 3 ).

公开(公告)号：DE10133873A1

公开(公告)日：2003-01-30

申请号：DE10133873

申请日：2001-07-12

Applicant: INFINEON TECHNOLOGIES AG

Inventor： WANG KAE-HORNG ,  STAUB RALF ,  KROENKE MATTHIAS

IPC: H01L21/60 ,  H01L21/768 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/283

Abstract: The invention relates to the production of one (or several) contacts on one or several active areas of a semiconductor disk, whereby one or several insulated control lines can be arranged on the active areas to be contacted. The control lines can, for example, be gate lines. The semiconductor element is produced in the following manner: a polysilicon layer is deposited on the semiconductor disk, the polysilicon layer is structured in order to produce a polysilicon contact over the active area, whereby the polysilicon contact covers the two control lines in an at least partial manner, a first insulator layer is applied to the semiconductor disk incorporating said polysilicon contact, the first insulator layer is partially removed to reveal the covering surface of the polysilicon contact and a metal layer is applied to the semiconductor disk for the electrical contacting of the polysilicon contact.