公开(公告)号：WO2004025693A3

公开(公告)日：2004-04-29

申请号：PCT/EP0308946

申请日：2003-08-12

Applicant: INFINEON TECHNOLOGIES AG ,  ENDERS GERHARD ,  FAUL JUERGEN ,  FISCHER BJOERN ,  HEINECK LARS ,  HIERLEMANN MATTHIAS ,  POPP MARTIN ,  VOIGT PETER

Inventor： ENDERS GERHARD ,  FAUL JUERGEN ,  FISCHER BJOERN ,  HEINECK LARS ,  HIERLEMANN MATTHIAS ,  POPP MARTIN ,  VOIGT PETER

IPC: H01L21/265 ,  H01L21/336 ,  H01L21/8242

CPC classification number: H01L27/10873 ,  H01L21/26586 ,  H01L27/10888 ,  H01L29/66492 ,  H01L29/6656 ,  H01L29/66659

Abstract: The invention relates to a method for the production of a semi-conductor structure comprising a plurality of gate stacks (GS1 - GS8) which are arranged on a semi-conductor substrate (1). Said method comprises the following steps: applying the gate-stack (GS1 - GS8) to a gate dielectric (5) via the semi-conductor substrate (1); implanting doping (100, 105, 110, 120, 130; 105''', 110''', 120''', 130''', 140''') which is self-adjusted in relation to the edges of the gate stack (GS1 - GS8); and forming an side wall oxide (40) on the free side walls of the gate stack (GS1 - GS8) while at the same time forming diffused doping areas (100', 110', 120', 130'; 110''', 120''', 130''', 140''') below the gate stack. The invention also relates to said type of semi-conductor structure.

Abstract translation: 本发明提供了一种用于生产具有多个栅极堆栈（GS1 - GS8）的半导体结构的半导体衬底（1）上通过以下步骤制备：将所述栅极堆叠 - 上的栅极电介质（GS1 GS8）（5 ）在半导体衬底上（1）; 注入掺杂剂（100，105，110，120，130; 105 '' '110' ''，120 '''，130' ''，140 ''“）自对准到栅叠层的边缘（GS1 - GS8 ）; 以及形成在所述栅极堆叠（GS1 - GS8）的暴露的侧壁上形成侧壁氧化物（40）与扩散掺杂区的同时形成（100 '110' ，120'，130 '; 110 '''，120' ''，130 “”栅极边缘下”，140' ‘’）。 本发明还提供这样的半导体结构。

公开(公告)号：DE102005036561B3

公开(公告)日：2007-02-08

申请号：DE102005036561

申请日：2005-08-03

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HEINECK LARS ,  POPP MARTIN

IPC: H01L21/8242

Abstract: A connecting structure connects a storage electrode of a trench capacitor and a selection transistor that are at least partially formed in a semiconductor substrate. The connecting structure includes a portion of an intermediate layer disposed adjacent to a surface of the storage electrode, and an electrically conducting material disposed adjacent to the intermediate layer and electrically connected to a semiconductor substrate surface portion adjacent to the selection transistor, wherein a part of the connecting structure is disposed above the semiconductor substrate surface so as to be adjacent to a horizontal substrate surface portion.

公开(公告)号：DE10353269B3

公开(公告)日：2005-05-04

申请号：DE10353269

申请日：2003-11-14

Applicant: INFINEON TECHNOLOGIES AG

Inventor： MOLL HANS-PETER ,  HEINECK LARS ,  SEITZ MIHEL ,  KUNDALGURKI SRIVATSA

IPC: H01L21/334 ,  H01L21/8242

Abstract: The production of a trench capacitor with an insulation collar (sic) in a substrate, which is electrically connected to the substrate via a trenched (sic) contact, especially for a semiconductor storage cell, and a selection transistor involves the provision of a trench in the substrate using a hard mask, a capacitor dielectric, an Si oxide liner, formation of a liner mask from part of the liner, and provision of an upper liner from undoped poly-Si or amorphous Si.

公开(公告)号：DE10314595A1

公开(公告)日：2004-10-21

申请号：DE10314595

申请日：2003-03-31

Applicant: INFINEON TECHNOLOGIES AG

Inventor： POPP MARTIN ,  HEINECK LARS

IPC: H01L21/8234 ,  H01L21/8239 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/8238

Abstract: Production of transistors (3,3') of different conductivity type in the first section of a surface of a semiconductor substrate (10) comprises forming a gate electrode layer (12) of first conductivity type doping on the substrate, producing gate structures (5) assigned to the transistors, forming a spacer structure and a covering structure to encapsulate the gate structures, using the encapsulated gate structures as masks and/or conducting structures for the self-adjusting contact of the transistors in a first section of the substrate, applying a protective layer (14) in the region of the first section, opening encapsulated gate structures by selectively removing the covering structures so that a part of the gate electrodes (7) of the gate structures is exposed, doping the gate electrode and the assigned source/drain regions (6,6') of the transistors with a dopant of second conductivity type.

公开(公告)号：DE102004019786B3

公开(公告)日：2005-09-01

申请号：DE102004019786

申请日：2004-04-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GRAF WERNER ,  HEINECK LARS

IPC: H01L21/60 ,  H01L21/768 ,  H01L21/8242 ,  H01L27/108

Abstract: Production of a first contact hole of a memory component comprises forming a semiconductor substrate (10) having a cell field region (20) and a logic region (30), producing an insulating layer (11) on the semiconductor surface, forming a sacrificial layer (12) on the insulating layer, depositing a fist mask layer, structuring the first mask layer to form first mask layer covers, anisotropically etching the sacrificial layer to expose the insulating layer, removing the first mask layer covers, depositing a second mask layer (16), structuring the second mask layer to form second mask layer covers, anisotropically etching the sacrificial layer to expose the insulating layer, removing the second mask layer covers, producing a filler layer between the blocks formed by the sacrificial layer, etching the sacrificial layer to remove the blocks in the filler layer, removing the exposed insulating layer, and filling contact opening regions with a conducting material.

公开(公告)号：DE10314274B3

公开(公告)日：2004-09-16

申请号：DE10314274

申请日：2003-03-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GRAF WERNER ,  HEINECK LARS ,  GENZ OLIVER ,  STAVREV MOMTCHIL ,  VOGT MIRKO

IPC: H01L21/60 ,  H01L21/768 ,  H01L21/8242 ,  H01L21/283

Abstract: Production of a first contact perforated surface in a storage device having storage cells comprises preparing a semiconductor substrate (1) with an arrangement of gate electrode strips (2) on the semiconductor surface, forming an insulating layer (3) on the semiconductor surface, forming a sacrificial layer on the insulating layer, forming material plugs on the sacrificial layer, producing a glass-like layer (8) exposing sacrificial layer blocks over contact openings between the gate electrode strips, etching the sacrificial material, removing the exposed insulating layer over the contact openings, and filling the contact opening regions with a conducting material (9). The sacrificial layer is formed by depositing a first sacrificial layer on the insulating layer, planarizing and depositing a second sacrificial layer.

公开(公告)号：DE102004060346B4

公开(公告)日：2006-10-19

申请号：DE102004060346

申请日：2004-12-15

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GRAF WERNER ,  HEINECK LARS ,  HORST JANA

IPC: H01L21/8239

Abstract: In a method for producing a semiconductor structure a semiconductor a substrate with a top surface is provided. A gate dielectric layer is provided on the top surface and on the gate dielectric layer is provided a memory cell array region with a first plurality of gate stacks and a peripheral element region with a second plurality of gate stacks. A dielectric layer is provided over the memory cell array region and the peripheral element region. A first source/drain implantation over the memory cell array region and the peripheral element region is carried out, a blocking mask over the memory cell array region is formed, the dielectric layer is removed using the blocking mask, and a second source/drain implantation over the memory cell array region and the peripheral element region is carried out, wherein the memory cell array region is protected by a mask.

公开(公告)号：DE102004060346A1

公开(公告)日：2006-07-20

申请号：DE102004060346

申请日：2004-12-15

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GRAF WERNER ,  HEINECK LARS ,  HORST JANA

IPC: H01L21/8239

Abstract: In a method for producing a semiconductor structure a semiconductor a substrate with a top surface is provided. A gate dielectric layer is provided on the top surface and on the gate dielectric layer is provided a memory cell array region with a first plurality of gate stacks and a peripheral element region with a second plurality of gate stacks. A dielectric layer is provided over the memory cell array region and the peripheral element region. A first source/drain implantation over the memory cell array region and the peripheral element region is carried out, a blocking mask over the memory cell array region is formed, the dielectric layer is removed using the blocking mask, and a second source/drain implantation over the memory cell array region and the peripheral element region is carried out, wherein the memory cell array region is protected by a mask.

公开(公告)号：DE10259634A1

公开(公告)日：2004-07-15

申请号：DE10259634

申请日：2002-12-18

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GRAF WERNER ,  HAFFNER HENNING ,  KOWALEWSKI JOHANNES ,  HEINECK LARS

IPC: H01L21/768 ,  H01L21/8242

Abstract: The invention relates to a method for production of contacts on a wafer, preferably with the aid of a lithographic process. The preferred embodiment provides a method which overcomes the disadvantages of the complex point/hole lithography process, and which avoids any increase in the process complexity. This method is achieved in that a strip structure extending over two layers is used to structure the contacts. The strip structure in the first layer is rotated at a predetermined angle with respect to the strip structure in the second layer, and the contacts are formed in the mutually overlapping areas of the strip structures in the two layers.

公开(公告)号：DE10314595B4

公开(公告)日：2006-05-04

申请号：DE10314595

申请日：2003-03-31

Applicant: INFINEON TECHNOLOGIES AG

Inventor： POPP MARTIN ,  HEINECK LARS

IPC: H01L21/8238 ,  H01L21/8234 ,  H01L21/8239 ,  H01L21/8242 ,  H01L27/108

Abstract: Production of transistors (3,3') of different conductivity type in the first section of a surface of a semiconductor substrate (10) comprises forming a gate electrode layer (12) of first conductivity type doping on the substrate, producing gate structures (5) assigned to the transistors, forming a spacer structure and a covering structure to encapsulate the gate structures, using the encapsulated gate structures as masks and/or conducting structures for the self-adjusting contact of the transistors in a first section of the substrate, applying a protective layer (14) in the region of the first section, opening encapsulated gate structures by selectively removing the covering structures so that a part of the gate electrodes (7) of the gate structures is exposed, doping the gate electrode and the assigned source/drain regions (6,6') of the transistors with a dopant of second conductivity type.