公开(公告)号：JP2002050701A

公开(公告)日：2002-02-15

申请号：JP2001197112

申请日：2001-06-28

Applicant: IBM ,  INFINEON TECHNOLOGIES CORP

Inventor： THOMAS W DAYER ,  LOUIS L SHEW ,  DAVID L KOTEKI ,  KARL J REEDENSU ,  GERHARD KUNKEL ,  LI HONG ,  YOUNG LIM ,  YON JIN PAKU

IPC: H01L21/768 ,  H01L21/8242 ,  H01L23/522 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To provide a DRAM cell which eliminates critical photolithorgraphic fabrication steps by merging stacked capacitor construction with electrical contacts, and to provide a method of fabrication thereof. SOLUTION: It is sufficient to conduct in one lithography step to form electrical contacts, because the stacked capacitors are on the same plane as bit lines and the stacked capacitors are located in a insulating material provided between the bit lines. Unlike the conventional capacitor-over-bit line(COB) DRAM cells having the capacitors on the bit lines, this DRAM cell having capacitors adjacent to the bit lines eliminates the need to have dedicated contacts in the capacitor, making it possible to realize higher capacitance with lower global topography.

公开(公告)号：JP2000269464A

公开(公告)日：2000-09-29

申请号：JP2000077068

申请日：2000-03-17

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： PARK YOUNG-JIN ,  RADENS CARL J ,  GERHARD KUNKEL

IPC: H01L21/8242 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To reduce an interference action between a buried strap and an access transistor channel of a semiconductor memory, by making a distance between a gate and the side of a trench larger than the minimum feature size. SOLUTION: A trench 102 forms an angle A at 0 degree to 45 degrees to a word line 104, and the angled portion 108 of an active area 106 forms a herringbone pattern to effectively lay out components such as the trench 102 and a contact 116. A portion 110 of the active area 106 is elongated to a value larger than feature size F to increase an average distance to reduce a dopant interference between the buried strap of the trench 102 and the word line 104. Therefore, this realizes a longer distance between the trench 102 and the bit line contact 116.

公开(公告)号：JP2000292929A

公开(公告)日：2000-10-20

申请号：JP2000092100

申请日：2000-03-29

Applicant: INFINEON TECHNOLOGIES CORP

Inventor： SCHROEDER UWE PAUL ,  GERHARD KUNKEL ,  ALOIS GUTMAN ,  SPULER BRUNO

IPC: G03F7/075 ,  G03F7/038 ,  G03F7/039 ,  G03F7/40 ,  H01L21/027

Abstract: PROBLEM TO BE SOLVED: To improve the etching resistance of a photoresist used in photolithography. SOLUTION: In the method of producing a photolithographic structure, the photoresist containing a photoactive component that responds to actinic radiation and a base resin having a protected active part is applied to a substrate, patternwise exposed to an effective dose of actinic radiation and exposed to a developer to form a patterned photoresist. The protected active part of the base resin is then made chemically reactive by deprotection, the formed reactive part is allowed to react with a silylating agent containing an etching protective component to incorporate the etching protective component into the structure of the base resin and the substrate is etched to product the objective photolithographic structure.

公开(公告)号：JP2000241989A

公开(公告)日：2000-09-08

申请号：JP2000038346

申请日：2000-02-16

Applicant: INFINEON TECHNOLOGIES CORP

Inventor： UWE PAUL SCHROEDER ,  GERHARD KUNKEL ,  ALOIS GUTMAN

IPC: H01L21/027 ,  G03F7/36 ,  G03F7/38 ,  G03F7/40

Abstract: PROBLEM TO BE SOLVED: To easily produce a photolithographic structure suitable for patterning in a far UV range. SOLUTION: A photoresist containing a base resin containing a protected active part that forms a reactive part under deprotection and a photoactive component readily sensitive to actinic radiation is applied to a substrate, patternwise exposed with an effective dose of the actinic radiation and exposed to a developer to form a patterned photoresist. The protected active part of the base resin is then deprotected to chemically form a reactive part, this reactive part is allowed to react with an aromatic ring-containing etch protector to incorporate the etch protector into the base resin and the substrate is etched.

公开(公告)号：JP2002313717A

公开(公告)日：2002-10-25

申请号：JP2002062283

申请日：2002-03-07

Applicant: INFINEON TECHNOLOGIES CORP

Inventor： GENZ OLIVER ,  PREUNINGER JURGEN ,  GERHARD KUNKEL

IPC: G03F7/20 ,  H01L21/027

Abstract: PROBLEM TO BE SOLVED: To provide a patterning process and a patterning apparatus which avoid restrictions in mask inspections and problems at alignment and compensates the line shortening, the problem in the prior part. SOLUTION: The process comprises a step of covering a wafer surface with a mask and a step of transferring a mask pattern to the wafer surface with a specified magnification. In the step of transferring the mask pattern the wafer is moved horizontally at a first velocity, while the mask is moved horizontally at a second velocity to expose a part of the wafer surface wherein the first and second velocities differ from each other and the ratio of the first velocity to the second velocity is different from the magnifying power.

公开(公告)号：JP2000323685A

公开(公告)日：2000-11-24

申请号：JP2000087033

申请日：2000-03-27

Applicant: INFINEON TECHNOLOGIES CORP

Inventor： LIAN JENNY ,  GERHARD KUNKEL

IPC: H01L27/105 ,  H01L21/02 ,  H01L21/768 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/108 ,  H01L27/10

Abstract: PROBLEM TO BE SOLVED: To obtain a method of manufacturing in which the source/drain region of an FET and a capacitor lower electrode are connected in small resistance without diffusion barrier in a memory cell provided with a stacked capacitor on a MOS field effect transistor (MOSFET). SOLUTION: A polysilicon plug 12 passing through a silicon oxide layer 14 on a silicon chip and connected in correspondence with a source/drain region of an FET is formed and a platinum layer is etched with a dielectric layer 16 as stopper to form a conductor 20. Then a high-dielectric layer 22, a capacitor upper electrode 24 and a dielectric layer 25 such as TEOS are layered, etching is carried out up to the polysilicon plug 12 leaving platinum conductors 20 to form an opening 32, a liner film 28 is formed, a conductive contact 30 is formed being insulated from the upper electrode 24, and the upper part is filled with TEOS 32 or the like.