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    Verbesserte Adressraum-Layoutrandomisierung
    5.
    发明专利
    Verbesserte Adressraum-Layoutrandomisierung 未知

    公开(公告)号：DE112017002277T5

    公开(公告)日：2019-01-17

    申请号：DE112017002277

    申请日：2017-06-02

    Applicant: INTEL CORP

    Inventor： GABOR RON ,  NUZMAN JOSEPH ,  STARK TOMER

    IPC: G06F21/12 ,  G06F12/02

    Abstract: Eine Ausführungsform stellt ein Gerät bereit. Das Gerät weist einen linearen Adressraum, Metadatenlogik und verbesserte Adressraum-Layoutrandomisierungs-(ASLR)-Logik auf. Der lineare Adressraum weist eine Metadaten-Datenstruktur auf. Die Metadatenlogik soll einen Metadatenwert erzeugen. Die verbesserte ASLR-Logik 138 soll Metadatenwerte und eine lineare Adresse zu einem Adresszeiger kombinieren und den Metadatenwert zu der Metadaten-Datenstruktur an einem Ort, zu dem mindestens ein Abschnitt der linearen Adresse zeigt, speichern. Der Adresszeiger entspricht einer scheinbaren Adresse in einem verbesserten Adressraum. Eine Größe des verbesserten Adressraums ist größer als eine Größe des linearen Adressraums.

    6.
    发明专利
    未知

    公开(公告)号：BRPI0904287A2

    公开(公告)日：2011-02-01

    申请号：BRPI0904287

    申请日：2009-10-30

    Applicant: INTEL CORP

    Inventor： VALENTINE ROBERT ,  RAPPOPORT LIHU ,  OUZIEL IDO ,  GABOR RON ,  RAGHUVANSHI PANKAJ

    IPC: G06F12/00

    Abstract: A technique to enable efficient instruction fusion within a computer system is disclosed. In one embodiment, a processor includes multiple cores, each including a first-level cache, a fetch circuit to fetch instructions, an instruction buffer (IBUF) to store instructions, a decode circuit to decode instructions, an execution circuit to execute decoded instructions, and an instruction fusion circuit to fuse a first instruction and a second instruction to form a fused instruction to be processed by the execution circuit as a single instruction, the instruction fusion occurring when both the first and second instructions have been stored in the IBUF prior to issuance to the decode circuit, and wherein the first instruction was the last instruction to be stored in the IBUF prior to the second instruction being stored in the IBUF, such that the first and second instructions are stored adjacently in the IBUF.

    7.
    发明专利
    未知

    公开(公告)号：DE102009051388A1

    公开(公告)日：2010-05-06

    申请号：DE102009051388

    申请日：2009-10-30

    Applicant: INTEL CORP

    Inventor： OUZIEL IDO ,  RAPPOPORT LIHU ,  VALENTINE ROBERT ,  GABOR RON ,  RAGHUVANSHI PANKAJ

    IPC: G06F9/22 ,  G06F9/32

    Abstract: A technique to enable efficient instruction fusion within a computer system is disclosed. In one embodiment, a processor includes multiple cores, each including a first-level cache, a fetch circuit to fetch instructions, an instruction buffer (IBUF) to store instructions, a decode circuit to decode instructions, an execution circuit to execute decoded instructions, and an instruction fusion circuit to fuse a first instruction and a second instruction to form a fused instruction to be processed by the execution circuit as a single instruction, the instruction fusion occurring when both the first and second instructions have been stored in the IBUF prior to issuance to the decode circuit, and wherein the first instruction was the last instruction to be stored in the IBUF prior to the second instruction being stored in the IBUF, such that the first and second instructions are stored adjacently in the IBUF.

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