公开(公告)号：JP2014059920A

公开(公告)日：2014-04-03

申请号：JP2014000371

申请日：2014-01-06

Applicant: Intel Corp ,  インテル コーポレイション

Inventor： WANG HONG ,  SHEN JOHN ,  ZHANG HONG ,  HANKINS RICHARD ,  HAMMARLUND PER ,  DION ROGERS ,  CHINYA GAUTHAM ,  PATEL BAIJU ,  KAUSHIK SHIV ,  BIGBEE BRYANT ,  SHEAFFER GAD ,  TALGAM YOAV ,  YOSEF YUVAL ,  HELD JAMES P

IPC: G06F9/38

CPC classification number: G06F9/30145 ,  G06F9/30 ,  G06F9/30181 ,  G06F9/3877 ,  G06F9/3879 ,  G06T1/20

Abstract: PROBLEM TO BE SOLVED: To provide a method, apparatus, system that enables effective communication between instruction set architecture-based sequencers having heterogeneous resources.SOLUTION: The method comprises: directly communicating a request from a user-level application to an accelerator coupled to a first instruction sequencer via the first instruction sequencer, where the accelerator comprises a heterogeneous resource with respect to the first instruction sequencer; providing the request to the accelerator via an exo-skeleton associated with the accelerator; and performing a first function in the accelerator in response to the request in parallel with a second function in the first instruction sequencer.

Abstract translation: 要解决的问题：提供一种使得能够在具有异构资源的指令集体系结构的定序器之间有效通信的方法，装置，系统。解决方案：该方法包括：将来自用户级应用的请求直接传达到耦合到 所述第一指令定序器经由所述第一指令定序器，其中所述加速器包括相对于所述第一指令定序器的异质资源; 通过与加速器相关联的外部骨架向加速器提供请求; 以及响应于与第一指令定序器中的第二功能并行的请求在加速器中执行第一功能。

公开(公告)号：JP2009110509A

公开(公告)日：2009-05-21

申请号：JP2008248759

申请日：2008-09-26

Applicant: Intel Corp ,  インテル コーポレイション

Inventor： FENGER RUSSELL J ,  AGGARWAL ANIL ,  KAUSHIK SHIV

IPC: G06F1/04 ,  G06F1/32 ,  G06F11/34

CPC classification number: G06F1/3203 ,  G06F1/3243 ,  Y02D10/126 ,  Y02D10/152

Abstract: PROBLEM TO BE SOLVED: To provide a system and method relating to adaptive power management using hardware feedback to select optimal processor frequencies and reduce power. SOLUTION: The adaptive power management using hardware feedback to select optimal processor frequencies and reduce power consumption is provided, and is intended to optimize a processor frequency and power consumption usage based on the hardware feedback and processor stall state behavior. COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：提供与使用硬件反馈的自适应功率管理相关的系统和方法，以选择最佳处理器频率并降低功率。 解决方案：提供使用硬件反馈来选择最佳处理器频率并降低功耗的自适应功率管理，并且旨在基于硬件反馈和处理器失速状态行为来优化处理器频率和功耗使用。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：JP2007102781A

公开(公告)日：2007-04-19

申请号：JP2006266590

申请日：2006-09-29

Applicant: Intel Corp ,  インテル・コーポレーション

Inventor： CHINYA GAUTHAM ,  WANG HONG ,  SETHI PRASHANT ,  KAUSHIK SHIV ,  BIGBEE BRYANT ,  SHEN JOHN ,  HANKINS RICHARD ,  ZOU XIANG ,  PATEL BAIJU ,  BRANDT JASON ,  AGGARWAL ANIL ,  REID JOHN

IPC: G06F9/50 ,  G06F9/48

CPC classification number: G06F9/3005 ,  G06F9/3009 ,  G06F9/3851 ,  G06F9/3861 ,  G06F9/3877 ,  G06F9/3885 ,  G06F9/461

Abstract: PROBLEM TO BE SOLVED: To provide a method for generating a persistent user-level thread.
SOLUTION: Embodiments of the invention provide a method of creating, based on an operating-system (OS)-scheduled thread running on an OS-visible sequencer and using an instruction set extension, a persistent user-level thread to run on an OS-sequestered sequencer independently of context switch activities on the OS-scheduled thread. The OS-scheduled thread and the persistent user-level thread may share a common virtual address space. Embodiments of the invention may also provide a method of causing a service thread running on an additional OS-visible sequencer to provide OS services to the persistent user-level thread. Embodiments of the invention may further provide apparatus, system, and machine-readable medium thereof.
COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供一种用于生成持久用户级线程的方法。 解决方案：本发明的实施例提供了一种基于在OS可见定序器上运行并使用指令集扩展的操作系统（OS）调度的线程来创建持久的用户级线程来运行的方法 独立于操作系统调度的线程上的上下文切换活动的OS隔离的定序器。 OS调度的线程和持久用户级线程可以共享公共的虚拟地址空间。 本发明的实施例还可以提供一种使服务线程在附加的OS可见定序器上运行以向持久用户级线程提供OS服务的方法。 本发明的实施例还可以提供其装置，系统和机器可读介质。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2011146077A

公开(公告)日：2011-07-28

申请号：JP2011101385

申请日：2011-04-28

Applicant: Intel Corp ,  インテル コーポレイション

Inventor： WANG HONG ,  SHEN JOHN ,  ZHANG HONG ,  HANKINS RICHARD ,  HAMMARLUND PER ,  RODGERS DION ,  CHINYA GAUTHAM ,  PATEL BAIJU ,  KAUSHIK SHIV ,  BIGBEE BRYANT ,  SHEAFFER GAD ,  TALGAM YOAV ,  YOSEF YUVAL ,  HELD JAMES P

IPC: G06F9/38

CPC classification number: G06F9/30145 ,  G06F9/30 ,  G06F9/30181 ,  G06F9/3877 ,  G06F9/3879 ,  G06T1/20

Abstract: PROBLEM TO BE SOLVED: To provide a method, a device, and a system for performing effective communication between instruction set architecture-based sequencers having heterogeneous resources. SOLUTION: The method includes: a step in which a first instruction sequencer is connected from a user-level application via the first instruction sequencer and a request is directly communicated to an accelerator having a heterogeneous resource with respect to the instruction sequencer; a step of providing the accelerator with the request via an exoskeleton related to the accelerator; and a step of performing a first function in parallel to a second function in the first instruction sequencer in response to the request in the accelerator. COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：提供一种用于在具有异构资源的指令集体系结构的定序器之间执行有效通信的方法，设备和系统。 该方法包括：第一指令定序器经由第一指令定序器从用户级应用连接并且请求直接传送到相对于指令定序器具有异构资源的加速器的步骤; 通过与加速器有关的外骨骼提供加速器请求的步骤; 以及响应于加速器中的请求，在第一指令定序器中执行与第二功能并行的第一功能的步骤。 版权所有（C）2011，JPO＆INPIT

公开(公告)号：JP2007183943A

公开(公告)日：2007-07-19

申请号：JP2006348294

申请日：2006-12-25

Applicant: Intel Corp ,  インテル コーポレイション

Inventor： WANG HONG ,  SHEN JOHN ,  ZHANG HONG ,  HANKINS RICHARD ,  HAMMARLUND PER ,  RODGERS DION ,  CHINYA GAUTHAM ,  PATEL BAIJU ,  KAUSHIK SHIV ,  BIGBEE BRYANT ,  SHEAFFER GAD ,  TALGAM YOAV ,  YOSEF YUVAL ,  HELD JAMES P

IPC: G06F9/38 ,  G06F9/50

CPC classification number: G06F9/30145 ,  G06F9/30 ,  G06F9/30181 ,  G06F9/3877 ,  G06F9/3879 ,  G06T1/20

Abstract: PROBLEM TO BE SOLVED: To provide a method, a device, and a system allowing effective communication between respective instruction set architecture base sequencers having heterogeneous resources. SOLUTION: This method is constructed of steps for: directly transmitting a request to an accelerator, which is connected via a first instruction sequencer and has heterogeneous resources about the first instruction sequencer, from a user level application to the first instruction sequencer; offering the request to the accelerator via an exoskeleton about the accelerator; and executing a first function in the accelerator in response to the request in parallel to a second function in the first instruction sequencer. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供一种允许具有异构资源的各个指令集架构基本定序器之间有效通信的方法，设备和系统。 解决方案：该方法由以下步骤构成：用于通过第一指令定序器将与第一指令定序器相关的异构资源从用户级应用程序直接传送到加速器的请求到第一指令定序器; 通过关于加速器的外骨骼向加速器提出要求; 以及响应于与第一指令定序器中的第二功能并行的请求，在加速器中执行第一功能。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：WO2006108169A3

公开(公告)日：2007-04-12

申请号：PCT/US2006013263

申请日：2006-04-05

Applicant: INTEL CORP ,  WANG HONG ,  CHINYA GAUTHAM ,  HANKINS RICHARD ,  RAKVIC RYAN ,  SHEN JOHN ,  KAUSHIK SHIV ,  BIGBEE BRYANT ,  HAMMARLUND PER ,  ZOU XIANG ,  BRANDT JASON ,  SETHI PRASHANT ,  REID JOHN ,  POULSEN DAVID ,  RODGERS SCOTT ,  CARMEAN DOUGLAS ,  PATEL BAIJU ,  SHAH SANJIV ,  HELD JAMES ,  ABEL JAMES

Inventor： WANG HONG ,  CHINYA GAUTHAM ,  HANKINS RICHARD ,  RAKVIC RYAN ,  SHEN JOHN ,  KAUSHIK SHIV ,  BIGBEE BRYANT ,  HAMMARLUND PER ,  ZOU XIANG ,  BRANDT JASON ,  SETHI PRASHANT ,  REID JOHN ,  POULSEN DAVID ,  RODGERS SCOTT ,  CARMEAN DOUGLAS ,  PATEL BAIJU ,  SHAH SANJIV ,  HELD JAMES ,  ABEL JAMES

IPC: G06F9/38 ,  G06F9/46

CPC classification number: G06F9/485 ,  G06F9/30043 ,  G06F9/30076 ,  G06F9/3851 ,  G06F9/3885 ,  G06F9/3891 ,  G06F9/461 ,  G06F9/4881

Abstract: Disclosed are embodiments of a system, methods and mechanism for management and translation of mapping between logical sequencer addresses and physical or logical sequencers in a multi-sequencer multithreading system. A mapping manager may manage assignment and mapping of logical sequencer addresses or pages to actual sequencers or frames of the system. Rationing logic associated with the mapping manager may take into account sequencer attributes when such mapping is performed Relocation logic associated with the mapping manager may manage spill and fill of context information to/from a backing store when re-mapping actual sequencers. Sequencers may be allocated singly, or may be allocated as part of partitioned blocks. The mapping manager may also include translation logic that provides an identifier for the mapped sequencer each time a logical sequencer address is used in a user program. Other embodiments are also described and claimed.

Abstract translation: 公开了用于在多序列器多线程系统中的逻辑定序器地址与物理或逻辑定序器之间的映射的管理和转换的系统，方法和机制的实施例。 映射管理器可以管理逻辑定序器地址或页面到系统的实际定序器或帧的分配和映射。 与映射管理器相关联的配给逻辑可以在执行这种映射时考虑定序器属性。当重新映射实际的定序器时，与映射管理器相关联的重定位逻辑可以管理向/从备份存储器的上下文信息的溢出和填充。 排序器可以单独分配，或者可以被分配为分区块的一部分。 映射管理器还可以包括每当在用户程序中使用逻辑定序器地址时为映射的定序器提供标识符的翻译逻辑。 还描述和要求保护其他实施例。

公开(公告)号：WO2006074059A2

公开(公告)日：2006-07-13

申请号：PCT/US2005047408

申请日：2005-12-28

Applicant: INTEL CORP ,  CHINYA GAUTHAM ,  WANG HONG ,  ZOU XIANG ,  KAUSHIK SHIV ,  BIGBEE BRYANT ,  SHEN JOHN ,  DIEP TRUNG ,  AGGARWAL ANIL ,  PATEL BAIJU V ,  HELD JAMES PAUL ,  SETHI PRASHANT ,  HANKINS RICHARD A ,  REID JOHN L

Inventor： CHINYA GAUTHAM ,  WANG HONG ,  ZOU XIANG ,  KAUSHIK SHIV ,  BIGBEE BRYANT ,  SHEN JOHN ,  DIEP TRUNG ,  AGGARWAL ANIL ,  PATEL BAIJU V ,  HELD JAMES PAUL ,  SETHI PRASHANT ,  HANKINS RICHARD A ,  REID JOHN L

CPC classification number: G06F9/45533 ,  G06F9/4881

Abstract: Method, apparatus and system embodiments to provide user-level creation, control and synchronization of OS-invisible "shreds" of execution via an abstraction layer for a system that includes one or more sequencers that are sequestered from operating system control. For at least one embodiment, the abstraction layer provides sequestration logic, proxy execution logic, transition detection and shred suspension logic, and sequencer arithmetic logic. Other embodiments are also described and claimed.

Abstract translation: 方法，装置和系统实施例，用于通过用于包括从操作系统控制隔离的一个或多个定序器的系统的抽象层来提供用户级别创建，控制和同步OS不可见的“碎片”。 对于至少一个实施例，抽象层提供封存逻辑，代理执行逻辑，转换检测和分片悬挂逻辑以及定序器算术逻辑。 还描述和要求保护其他实施例。

公开(公告)号：WO2004031950A2

公开(公告)日：2004-04-15

申请号：PCT/US0329786

申请日：2003-09-19

Applicant: INTEL CORP

Inventor： KAUSHIK SHIV ,  CROSSLAND JAMES ,  KUMAR MOHAN ,  RANKIN LINDA ,  O'SHEA DAVID

IPC: G06F9/445

CPC classification number: G06F9/4411

Abstract: An apparatus and system may include a peripheral device, such as an interrupt controller or Peripheral Component Interconnect (PCI) bridge device, having a memory-mapped legacy register and a PCI dummy register. The legacy register may be accessed by a Basic Input/Output System (BIOS) as part of a power-on initialization sequence for the peripheral device, and the dummy register may be accessed during a hot-plug operation using code executed by an Operating System (OS). An article, including a machine-accessible medium, may contain data capable of causing a machine to carry out a method of representing a peripheral device which includes identifying the peripheral device as a legacy device in a name space, such as an Advanced Configuration and Power Interface (ACPI) name space, and identifying the peripheral device as a dummy PCI device capable of being accessed during a hot-plug operation.

Abstract translation: 装置和系统可以包括具有存储器映射的遗留寄存器和PCI伪寄存器的外围设备，诸如中断控制器或外围组件互连（PCI）桥接器件。 传统寄存器可以由基本输入/输出系统（BIOS）作为外围设备的上电初始化序列的一部分访问，并且可以在热插拔操作期间使用由操作系统执行的代码来访问虚拟寄存器 （OS）。 包括机器可访问介质的文章可以包含能够使机器执行表示外围设备的方法的数据，其包括将外围设备识别为名称空间中的传统设备，诸如高级配置和电源 接口（ACPI）名称空间，并将外围设备识别为能够在热插拔操作期间被访问的虚拟PCI设备。

公开(公告)号：DE112006000807T5

公开(公告)日：2008-01-31

申请号：DE112006000807

申请日：2006-04-05

Applicant: INTEL CORP

Inventor： WANG HONG ,  CHINYA GAUTHAM ,  HANKINS RICHARD ,  RAKVIC RYAN ,  SHEN JOHN ,  KAUSHIK SHIV ,  BIGBEE BRYANT ,  HAMMARLUND PER ,  ZOU XIANG ,  BRANDT JASON ,  SETHI PRASHANT ,  REID JOHN ,  POULSEN DAVID ,  RODGERS SCOTT ,  CARMEAN DOUGLAS ,  PATEL BAIJU ,  SHAH SANJIV ,  HELD JAMES ,  ABEL JAMES

IPC: G06F9/38

Abstract: Disclosed are embodiments of a system, methods and mechanism for management and translation of mapping between logical sequencer addresses and physical or logical sequencers in a multi-sequencer multithreading system. A mapping manager may manage assignment and mapping of logical sequencer addresses or pages to actual sequencers or frames of the system. Rationing logic associated with the mapping manager may take into account sequencer attributes when such mapping is performed Relocation logic associated with the mapping manager may manage spill and fill of context information to/from a backing store when re-mapping actual sequencers. Sequencers may be allocated singly, or may be allocated as part of partitioned blocks. The mapping manager may also include translation logic that provides an identifier for the mapped sequencer each time a logical sequencer address is used in a user program. Other embodiments are also described and claimed.

公开(公告)号：DE112006000807B4

公开(公告)日：2014-01-30

申请号：DE112006000807

申请日：2006-04-05

Applicant: INTEL CORP

Inventor： WANG HONG ,  CHINYA GAUTHAM ,  HANKINS RICHARD ,  RAKVIC RYAN ,  SHEN JOHN ,  KAUSHIK SHIV ,  BIGBEE BRYANT ,  HAMMARLUND PER ,  ZOU XIANG ,  BRANDT JASON ,  SETHI PRASHANT ,  REID JOHN ,  POULSEN DAVID ,  RODGERS SCOTT ,  CARMEAN DOUGLAS ,  PATEL BAIJU ,  SHAH SANJIV ,  HELD JAMES ,  ABEL JAMES

IPC: G06F9/38

Abstract: Ein Verfahren zur Verwaltung von Sequenzeradressen und zur Ausführung durch einen Mapping-Manager (302, 402, 502, 1020, 1670) in einem Multisequenzer-Multithreadingsystem (110, 115, 150, 170), umfassend: Durch eine Übersetzungslogik (486) Empfangen einer logischen Sequenzeradresse, die in einem Anwenderbefehl für einen logischen Sequenzer eines Prozessors angegeben ist, wobei der logische Sequenzer wenigstens einen durch ein Betriebssystem verwalteten ersten logischen Sequenzer (1620) und eine Vielzahl zweite logische Sequenzer (1640) umfasst, die durch Anwendercode des ersten Sequenzers verwaltet werden; Prüfen einer Mappingstruktur (580, 1010) auf bereits gespeicherte Zuordnung der logischen Sequenzeradresse zu wenigstens einer aus einer Vielzahl von physikalischen Sequenzeradressen einer Vielzahl physikalischer Sequenzer mit Ausführungsressourcen (1680) des Systems, wobei die Mappingstruktur (580, 1010) eine oder mehrere Seitentabellen umfasst, die jeweils einem Thread entsprechen, wobei Einträge der Seitentabellen in einer Übersetzungsbeschleunigungsstruktur gespeichert werden, die dem physikalischen Sequenzer dieses Threads zugeordnet ist ...