公开(公告)号：WO2006108169A3

公开(公告)日：2007-04-12

申请号：PCT/US2006013263

申请日：2006-04-05

Applicant: INTEL CORP ,  WANG HONG ,  CHINYA GAUTHAM ,  HANKINS RICHARD ,  RAKVIC RYAN ,  SHEN JOHN ,  KAUSHIK SHIV ,  BIGBEE BRYANT ,  HAMMARLUND PER ,  ZOU XIANG ,  BRANDT JASON ,  SETHI PRASHANT ,  REID JOHN ,  POULSEN DAVID ,  RODGERS SCOTT ,  CARMEAN DOUGLAS ,  PATEL BAIJU ,  SHAH SANJIV ,  HELD JAMES ,  ABEL JAMES

Inventor： WANG HONG ,  CHINYA GAUTHAM ,  HANKINS RICHARD ,  RAKVIC RYAN ,  SHEN JOHN ,  KAUSHIK SHIV ,  BIGBEE BRYANT ,  HAMMARLUND PER ,  ZOU XIANG ,  BRANDT JASON ,  SETHI PRASHANT ,  REID JOHN ,  POULSEN DAVID ,  RODGERS SCOTT ,  CARMEAN DOUGLAS ,  PATEL BAIJU ,  SHAH SANJIV ,  HELD JAMES ,  ABEL JAMES

IPC: G06F9/38 ,  G06F9/46

CPC classification number: G06F9/485 ,  G06F9/30043 ,  G06F9/30076 ,  G06F9/3851 ,  G06F9/3885 ,  G06F9/3891 ,  G06F9/461 ,  G06F9/4881

Abstract: Disclosed are embodiments of a system, methods and mechanism for management and translation of mapping between logical sequencer addresses and physical or logical sequencers in a multi-sequencer multithreading system. A mapping manager may manage assignment and mapping of logical sequencer addresses or pages to actual sequencers or frames of the system. Rationing logic associated with the mapping manager may take into account sequencer attributes when such mapping is performed Relocation logic associated with the mapping manager may manage spill and fill of context information to/from a backing store when re-mapping actual sequencers. Sequencers may be allocated singly, or may be allocated as part of partitioned blocks. The mapping manager may also include translation logic that provides an identifier for the mapped sequencer each time a logical sequencer address is used in a user program. Other embodiments are also described and claimed.

Abstract translation: 公开了用于在多序列器多线程系统中的逻辑定序器地址与物理或逻辑定序器之间的映射的管理和转换的系统，方法和机制的实施例。 映射管理器可以管理逻辑定序器地址或页面到系统的实际定序器或帧的分配和映射。 与映射管理器相关联的配给逻辑可以在执行这种映射时考虑定序器属性。当重新映射实际的定序器时，与映射管理器相关联的重定位逻辑可以管理向/从备份存储器的上下文信息的溢出和填充。 排序器可以单独分配，或者可以被分配为分区块的一部分。 映射管理器还可以包括每当在用户程序中使用逻辑定序器地址时为映射的定序器提供标识符的翻译逻辑。 还描述和要求保护其他实施例。

公开(公告)号：DE112006000807T5

公开(公告)日：2008-01-31

申请号：DE112006000807

申请日：2006-04-05

Applicant: INTEL CORP

Inventor： WANG HONG ,  CHINYA GAUTHAM ,  HANKINS RICHARD ,  RAKVIC RYAN ,  SHEN JOHN ,  KAUSHIK SHIV ,  BIGBEE BRYANT ,  HAMMARLUND PER ,  ZOU XIANG ,  BRANDT JASON ,  SETHI PRASHANT ,  REID JOHN ,  POULSEN DAVID ,  RODGERS SCOTT ,  CARMEAN DOUGLAS ,  PATEL BAIJU ,  SHAH SANJIV ,  HELD JAMES ,  ABEL JAMES

IPC: G06F9/38

Abstract: Disclosed are embodiments of a system, methods and mechanism for management and translation of mapping between logical sequencer addresses and physical or logical sequencers in a multi-sequencer multithreading system. A mapping manager may manage assignment and mapping of logical sequencer addresses or pages to actual sequencers or frames of the system. Rationing logic associated with the mapping manager may take into account sequencer attributes when such mapping is performed Relocation logic associated with the mapping manager may manage spill and fill of context information to/from a backing store when re-mapping actual sequencers. Sequencers may be allocated singly, or may be allocated as part of partitioned blocks. The mapping manager may also include translation logic that provides an identifier for the mapped sequencer each time a logical sequencer address is used in a user program. Other embodiments are also described and claimed.

公开(公告)号：DE112006000807B4

公开(公告)日：2014-01-30

申请号：DE112006000807

申请日：2006-04-05

Applicant: INTEL CORP

Inventor： WANG HONG ,  CHINYA GAUTHAM ,  HANKINS RICHARD ,  RAKVIC RYAN ,  SHEN JOHN ,  KAUSHIK SHIV ,  BIGBEE BRYANT ,  HAMMARLUND PER ,  ZOU XIANG ,  BRANDT JASON ,  SETHI PRASHANT ,  REID JOHN ,  POULSEN DAVID ,  RODGERS SCOTT ,  CARMEAN DOUGLAS ,  PATEL BAIJU ,  SHAH SANJIV ,  HELD JAMES ,  ABEL JAMES

IPC: G06F9/38

Abstract: Ein Verfahren zur Verwaltung von Sequenzeradressen und zur Ausführung durch einen Mapping-Manager (302, 402, 502, 1020, 1670) in einem Multisequenzer-Multithreadingsystem (110, 115, 150, 170), umfassend: Durch eine Übersetzungslogik (486) Empfangen einer logischen Sequenzeradresse, die in einem Anwenderbefehl für einen logischen Sequenzer eines Prozessors angegeben ist, wobei der logische Sequenzer wenigstens einen durch ein Betriebssystem verwalteten ersten logischen Sequenzer (1620) und eine Vielzahl zweite logische Sequenzer (1640) umfasst, die durch Anwendercode des ersten Sequenzers verwaltet werden; Prüfen einer Mappingstruktur (580, 1010) auf bereits gespeicherte Zuordnung der logischen Sequenzeradresse zu wenigstens einer aus einer Vielzahl von physikalischen Sequenzeradressen einer Vielzahl physikalischer Sequenzer mit Ausführungsressourcen (1680) des Systems, wobei die Mappingstruktur (580, 1010) eine oder mehrere Seitentabellen umfasst, die jeweils einem Thread entsprechen, wobei Einträge der Seitentabellen in einer Übersetzungsbeschleunigungsstruktur gespeichert werden, die dem physikalischen Sequenzer dieses Threads zugeordnet ist ...