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公开(公告)号:JPS6114798A
公开(公告)日:1986-01-22
申请号:JP1564885
申请日:1985-01-31
Applicant: Ibm
Inventor: LEVINE ERNEST NORMAN , LIPSCHUTZ LEWIS DRUCKER , QUINONES HORATIO
CPC classification number: H01L24/81 , H01L2224/81801 , H01L2924/01006 , H01L2924/01013 , H01L2924/01033 , H01L2924/014 , H01L2924/10253 , H01L2924/14 , H01L2924/15787 , H01L2924/3511 , H05K3/3436 , H01L2924/00
Abstract: Arrays of solder interconnections between a semiconductor device (10) and a supporting substrate (12) are annealed for a time in excess of one or several days below the solder melting temperature to relief stress and improve the fatigue failure of the interconnections.
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公开(公告)号:JPS61177738A
公开(公告)日:1986-08-09
申请号:JP20460485
申请日:1985-09-18
Applicant: IBM
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公开(公告)号:CA1224576A
公开(公告)日:1987-07-21
申请号:CA483512
申请日:1985-06-07
Applicant: IBM
Inventor: BECKHAM KEITH F , KOLMAN ANNE E , MCGUIRE KATHLEEN M , PUTTLITZ KARL J , QUINONES HORATIO
Abstract: Solder Interconnection Structure For Joining Semiconductor Devices To Substrates That Have Improved Fatigue Life, And Process For Making An improved solder interconnection for forming I/O connections between an integrated semiconductor device and a support substrate having a plurality of solder connections arranged in an area array joining a set of I/O's on a flat surface of the semiconductor device to a corresponding set of solder wettable pads on a substrate, the improvement being a band of dielectric organic material disposed between and bonded to the device and substrate embedding at least an outer row of solder connections leaving the center inner solder connections and the adjacent top and bottom surfaces free of dielectric material.
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公开(公告)号:DE3675554D1
公开(公告)日:1990-12-20
申请号:DE3675554
申请日:1986-01-17
Applicant: IBM
Inventor: BECKHAM KEITH FOWLER , KOLMAN ANNE ELIZABETH , MCGUIRE KATHLEEN MARY , PUTTLITZ KARL JOSEPH , QUINONES HORATIO
Abstract: An improved solder interconnection for forming 1/0 connections between an integrated semiconductor device and a support substrate having a plurality of solder connections arranged in an area array joining a set of I/O's on a flat surface of the semiconductor device to a corresponding set of solder wettable pads on a substrate, the improvement being a band of dielectric organic material disposed between and bonded to the device and substrate embedding at least an outer row of solder connections leaving the center inner solder connections and the adjacent top and bottom surfaces free of dielectric material.
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公开(公告)号:CA2006229A1
公开(公告)日:1990-09-14
申请号:CA2006229
申请日:1989-12-20
Applicant: IBM
Inventor: BECKHAM KEITH F , CHALLENER DAVID C , GUPTA ARUNAVA , HARVILCHUCK JOSEPH M , LEAS JAMES M , LLOYD JAMES R , LONG DAVID C , QUINONES HORATIO , SESHAN KRISHNA , SHATZKES MORRIS
IPC: B23K26/00 , H01L21/3205 , H01L21/82 , H01L23/52 , H01L23/525 , H05K3/22 , G01R31/26
Abstract: METHOD AND APPARATUS FOR CAUSING AN OPEN CIRCUIT IN A CONDUCTIVE LINE A method for causing an open circuit in an electrical conductor is provided, including the steps of: conducting a direct current through the conductor; and applying heat at a selected location on the conductor whereat it is desired to cause the open circuit of the conductor. . FI9-88-027
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公开(公告)号:DE3570154D1
公开(公告)日:1989-06-15
申请号:DE3570154
申请日:1985-06-13
Applicant: IBM
Inventor: LEVINE ERNEST NORMAN , LIPSCHUTZ LEWIS DRUCKER , QUINONES HORATIO
IPC: H05K3/34 , C25D21/14 , H01L21/60 , H01L21/92 , H01L21/324
Abstract: Arrays of solder interconnections between a semiconductor device (10) and a supporting substrate (12) are annealed for a time in excess of one or several days below the solder melting temperature to relief stress and improve the fatigue failure of the interconnections.
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