公开(公告)号：US3345596A

公开(公告)日：1967-10-03

申请号：US50680365

申请日：1965-11-08

Applicant: IBM

Inventor： DELANEY RONALD A ,  PUTTLITZ KARL J

IPC: G01N27/12 ,  H01B1/00 ,  H01C17/065

CPC classification number: H01C17/06533 ,  G01N27/121 ,  H01B1/00

公开(公告)号：DE2860348D1

公开(公告)日：1981-02-12

申请号：DE2860348

申请日：1978-11-13

Applicant: IBM

Inventor： MEYEN ROBERT H ,  PUTTLITZ KARL J ,  SCHINK KARL ,  WENSKUS HERBERT

IPC: H05K3/34 ,  B23K1/005 ,  H01L21/60 ,  H05K13/00 ,  H01L21/68 ,  B23K1/00

Abstract: An individual chip soldering machine comprising an infrared heat source (42) enclosed by an energy concentrating reflector (44). The energy outlet from the reflector is covered by a quartz plate (46). A shield member (48) defines a second energy outlet (13). Vacuum suction can be admitted to the chamber (47) to hold a chip against the wall (50) of the outlet (13). The substrate (10) is mounted on a preheating chamber (126) comprising infrared heater (120) and surrogate substrate (11). The heater (120) is energised from power source (134) controlled by controller (132) responsive to the output of thermocouple (130) attached to substrate (11). In use the reflector is moved towards the substrate (10) until the outlet (13) contacts a chip on the substrate (10). The reflector is then backed off a predetermined distance which is such that the focal plane of the heat energy focused by the reflector (44), coincides with the solder containing space between the chip and the substrate.

公开(公告)号：CA2084685C

公开(公告)日：1996-01-16

申请号：CA2084685

申请日：1990-10-16

Applicant: IBM

Inventor： AGARWALA BIRENDRA N ,  AHSAN AZIZ M ,  BROSS ARTHUR ,  CHADURJIAN MARK F ,  KOOPMAN NICHOLAS G ,  LEE LI-CHUNG ,  PUTTLITZ KARL J ,  RAY SUDIPTA K ,  RYAN JAMES G ,  SCHAEFER JOSEPH G ,  SRIVASTAVA KAMALESH K ,  TOTTA PAUL A ,  WALTON ERICK G ,  WIRSING ADOLF E

IPC: H01L21/60 ,  H01L23/485 ,  H05K3/34 ,  H01L23/488 ,  H01L23/50

Abstract: The present invention relates generally to a new interconnection and a method for making the same, and more particularly, to an elongated solder interconnection and a method for making the same. On an electronic carrier (12) a pad (14) is formed on which a solder mass (16) is deposited and capped with a metal layer (19), thereby forming an elongated solder interconnection. A further elongated solder interconnection can now be formed by forming a second solder mass (26) on the first solder mass that has been capped by a metal layer. Additional elongated solder interconnection can be formed by capping the preceding solder mass and/or the last solder mass with a metal capping layer. Alternatively, the encapsulating layer can be in the form of a sidewall spacer formed on the sidewalls of the solder mass.

公开(公告)号：CA2084685A1

公开(公告)日：1991-12-20

申请号：CA2084685

申请日：1990-10-16

Applicant: IBM

Inventor： AGARWALA BIRENDRA N ,  AHSAN AZIZ M ,  BROSS ARTHUR ,  CHADURJIAN MARK F ,  KOOPMAN NICHOLAS G ,  LEE LI-CHUNG ,  PUTTLITZ KARL J ,  RAY SUDIPTA K ,  RYAN JAMES G ,  SCHAEFER JOSEPH G ,  SRIVASTAVA KAMALESH K ,  TOTTA PAUL A ,  WALTON ERICK G ,  WIRSING ADOLF E

IPC: H01L21/60 ,  H01L23/485 ,  H05K3/34

Abstract: The present invention relates generally to a new interconnection and a method for making the same, and more particularly, to an elongated solder interconnection and a method for making the same. On an electronic carrier, a pad is formed on which a solder mass is deposited and capped with a metal layer, thereby forming an elongated solder interconnection. A further elongated solder interconnection can now be formed by forming a second solder mass on the first solder mass that has been capped by a metal layer. Additional elongated solder interconnection can be formed by capping the preceding solder mass and/or the last solder mass with a metal capping layer. Alternatively, the encapsulating layer can be in the form of a sidewall spacer formed on the sidewalls of the solder mass.

公开(公告)号：CA1224576A

公开(公告)日：1987-07-21

申请号：CA483512

申请日：1985-06-07

Applicant: IBM

Inventor： BECKHAM KEITH F ,  KOLMAN ANNE E ,  MCGUIRE KATHLEEN M ,  PUTTLITZ KARL J ,  QUINONES HORATIO

IPC: H01L21/60 ,  H01L21/56 ,  H05K3/28 ,  H05K3/34

Abstract: Solder Interconnection Structure For Joining Semiconductor Devices To Substrates That Have Improved Fatigue Life, And Process For Making An improved solder interconnection for forming I/O connections between an integrated semiconductor device and a support substrate having a plurality of solder connections arranged in an area array joining a set of I/O's on a flat surface of the semiconductor device to a corresponding set of solder wettable pads on a substrate, the improvement being a band of dielectric organic material disposed between and bonded to the device and substrate embedding at least an outer row of solder connections leaving the center inner solder connections and the adjacent top and bottom surfaces free of dielectric material.

公开(公告)号：CA850904A

公开(公告)日：1970-09-08

申请号：CA850904D

Applicant: IBM

Inventor： PUTTLITZ KARL J ,  DELANEY RONALD A