公开(公告)号：WO2004084266A3

公开(公告)日：2005-05-06

申请号：PCT/US2004007527

申请日：2004-03-10

Applicant: LAM RES CORP ,  LOHOKARE SHRIKANT P ,  BAILEY ANDREW D III ,  HEMKER DAVID ,  COOK JOEL M

Inventor： LOHOKARE SHRIKANT P ,  BAILEY ANDREW D III ,  HEMKER DAVID ,  COOK JOEL M

IPC: B44C1/22 ,  H01L20060101 ,  H01L21/302 ,  H01L21/304 ,  H01L21/311 ,  H01L21/321 ,  H01L21/3213 ,  H01L21/4763 ,  H01L21/768 ,  H01L33/00 ,  H01L21/4768

CPC classification number: H01L21/7684 ,  H01L21/31116 ,  H01L21/32115 ,  H01L21/32135 ,  H01L21/32136

Abstract: A system and method for planarizing a patterned semiconductor substrate (100) includes receiving a patterned semiconductor substrate. The patterned semiconductor substrate (100) having a conductive interconnect material (120) filling multiple of features in the pattern. The conductive interconnect material has an overburden portion (112). The overburden portion has a localized non-uniformity. A bulk portion of the overburden portion is removed to planarize the overburden portion (120). The substantially locally planarized overburden portion is mapped to determine a global non-uniformity. The substantially locally planarized overburden portion is etched to substantially remove the global non-uniformity.

Abstract translation: 用于平坦化图案化半导体衬底（100）的系统和方法包括接收图案化的半导体衬底。 图案化半导体衬底（100）具有填充图案中的多个特征的导电互连材料（120）。 导电互连材料具有覆盖层部分（112）。 覆盖层部分具有局部不均匀性。 去除覆盖层部分的主体部分以平坦化上覆层部分（120）。 映射基本上局部平坦化的覆盖层部分以确定全局不均匀性。 基本上局部平坦化的覆盖层部分被蚀刻以基本上去除全局不均匀性。

公开(公告)号：WO2004084267A3

公开(公告)日：2006-02-23

申请号：PCT/US2004007530

申请日：2004-03-10

Applicant: LAM RES CORP ,  LOHOKARE SHRIKANT P ,  BAILEY ANDREW D III ,  HEMKER DAVID ,  COOK JOEL M

Inventor： LOHOKARE SHRIKANT P ,  BAILEY ANDREW D III ,  HEMKER DAVID ,  COOK JOEL M

IPC: H01L21/3105 ,  H01L21/321 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/311

CPC classification number: H01L21/32135 ,  H01L21/32115 ,  H01L21/32136 ,  H01L21/7684

Abstract: A system and method for planarizing a patterned semiconductor substrate includes receiving a patterned semiconductor substrate (100). The patterned semiconductor substrate includes a conductive interconnect material (120) filling multiple of features (102, 104,106) in the pattern. The conductive interconnect material having an overburden portion (112). The overburden portion (112) includes a localized non-uniformity (indicated in variations 114, 116, 118). An additional layer (202) is formed an the overburden portion. The additional layer and the overburden portion are planarized. The planarizing process substantially entirely removes the additional layer.

Abstract translation: 用于平坦化图案化半导体衬底的系统和方法包括接收图案化的半导体衬底（100）。 图案化的半导体衬底包括以图案填充多个特征（102,104,106）的导电互连材料（120）。 所述导电互连材料具有覆盖层部分（112）。 覆盖层部分（112）包括局部不均匀性（在变化形式114,116,118中指示）。 附加层（202）形成为上覆层部分。 附加层和覆盖层部分被平坦化。 平坦化工艺基本上完全除去附加层。

公开(公告)号：EP1604393A4

公开(公告)日：2009-11-11

申请号：EP04719313

申请日：2004-03-10

Applicant: LAM RES CORP

Inventor： LOHOKARE SHRIKANT P ,  BAILEY ANDREW D III ,  HEMKER DAVID ,  COOK JOEL M

IPC: B44C1/22 ,  H01L20060101 ,  H01L21/302 ,  H01L21/304 ,  H01L21/311 ,  H01L21/321 ,  H01L21/3213 ,  H01L21/4763 ,  H01L21/768 ,  H01L33/00

CPC classification number: H01L21/7684 ,  H01L21/31116 ,  H01L21/32115 ,  H01L21/32135 ,  H01L21/32136

公开(公告)号：EP1611599A4

公开(公告)日：2007-06-13

申请号：EP04719319

申请日：2004-03-10

Applicant: LAM RES CORP

Inventor： LOHOKARE SHRIKANT P ,  BAILEY ANDREW D III ,  HEMKER DAVID ,  COOK JOEL M

IPC: H01L21/321 ,  H01L21/3105 ,  H01L21/3213 ,  H01L21/768

CPC classification number: H01L21/32135 ,  H01L21/32115 ,  H01L21/32136 ,  H01L21/7684

Abstract: A system and method for planarizing a patterned semiconductor substrate includes receiving a patterned semiconductor substrate. The patterned semiconductor substrate having a conductive interconnect material filling multiple of features in the pattern. The conductive interconnect material having an overburden portion. The overburden portion includes a localized non-uniformity. An additional layer is formed an the overburden portion. The additional layer and the overburden portion are planarized. The planarizing process substantially entirely removes the additional layer.

公开(公告)号：AT230811T

公开(公告)日：2003-01-15

申请号：AT97925746

申请日：1997-06-02

Applicant: LAM RES CORP

Inventor： WICKER THOMAS E ,  COOK JOEL M ,  MARASCHIN ROBERT A ,  KENNEDY WILLIAM S ,  BENJAMIN NEIL

IPC: C23C16/44 ,  C23C16/455 ,  C23C16/50 ,  C23C16/505 ,  C23C16/507 ,  H01J37/32 ,  H01L21/205 ,  H01L21/302

Abstract: A plasma processing chamber includes a substrate holder and a dielectric member such as a dielectric window or gas distribution plate having an interior surface facing the substrate holder, the interior surface being maintained below a threshold temperature to minimize process drift during processing of substrates. The chamber can include an antenna which inductively couples RF energy through the dielectric member to energize process gas into a plasma state. The antenna can include a channel through which a temperature controlling fluid, which has been cooled by a closed circuit temperature controller, is passed. The control of the temperature of the interior surface minimizes process drift and degradation of the quality of the processed substrates during sequential batch processing of substrates such as during oxide etching of semiconductor wafers.

公开(公告)号：SG149018A1

公开(公告)日：2009-01-29

申请号：SG2008092041

申请日：2004-12-07

Applicant: LAM RES CORP

Inventor： DORDI YEZDI ,  BOYD JOHN ,  THIE WILLIAM ,  MARASCHIN BOB ,  REDEKER FRED C ,  COOK JOEL M

IPC: C23C18/16 ,  C23C18/54

Abstract: METHOD AND APPARATUS FOR MATERIAL DEPOSITION A method and an apparatus are provided for selective heating of a surface of a wafer exposed to an electroless plating solution. Selective heating by a radiant energy source causes a temperature increase at an interface between the wafer surface and the electroless plating solution. This temperature increase causes a plating reaction to occur at the wafer surface. Thus, material is deposited on the wafer surface through an electroless plating reaction that is initiated and controlled by varying the temperature of the wafer surface using an appropriately defined radiant energy source. Additionally, a planar member can be positioned over and proximate to the wafer surface to entrap electroless plating solution between the planar member and the wafer surface. Material deposited through the plating reactions forms a planarizing layer that conforms to a planarity of the planar member. Fig 2A

公开(公告)号：IL170852A

公开(公告)日：2010-06-30

申请号：IL17085205

申请日：2005-09-13

Applicant: III ANDREW D BAILEY ,  LAM RES CORP ,  LOHOKARE SHRIKANT P ,  HEMKER DAVID ,  COOK JOEL M

Inventor： III ANDREW D BAILEY ,  LOHOKARE SHRIKANT P ,  HEMKER DAVID ,  COOK JOEL M

IPC: B44C1/22 ,  H01L20060101 ,  H01L21/302 ,  H01L21/304 ,  H01L21/311 ,  H01L21/321 ,  H01L21/3213 ,  H01L21/4763 ,  H01L21/768 ,  H01L33/00

Abstract: A system and method for planarizing a patterned semiconductor substrate includes receiving a patterned semiconductor substrate. The patterned semiconductor substrate having a conductive interconnect material filling multiple of features in the pattern. The conductive interconnect material having an overburden portion. The overburden portion having a localized non-uniformity. A bulk portion of the overburden portion is removed to planarize the overburden portion. The substantially locally planarized overburden portion is mapped to determine a global non-uniformity. The substantially locally planarized overburden portion is etched to substantially remove the global non-uniformity.

公开(公告)号：SG149019A1

公开(公告)日：2009-01-29

申请号：SG2008092058

申请日：2004-12-07

Applicant: LAM RES CORP

Inventor： DORDI YEZDI ,  BOYD JOHN ,  THIE WILLIAM ,  MARASCHIN BOB ,  REDEKER FRED C ,  COOK JOEL M

IPC: C23C18/16 ,  C23C18/54

Abstract: METHOD AND APPARATUS FOR MATERIAL DEPOSITION A method and an apparatus are provided for selective heating of a surface of a wafer exposed to an electroless plating solution. Selective heating by a radiant energy source causes a temperature increase at an interface between the wafer surface and the electroless plating solution. This temperature increase causes a plating reaction to occur at the wafer surface. Thus, material is deposited on the wafer surface through an electroless plating reaction that is initiated and controlled by varying the temperature of the wafer surface using an appropriately defined radiant energy source. Additionally, a planar member can be positioned over and proximate to the wafer surface to entrap electroless plating solution between the planar member and the wafer surface. Material deposited through the plating reactions forms a planarizing layer that conforms to a planarity of the planar member. Fig 2A

公开(公告)号：SG182190A1

公开(公告)日：2012-07-30

申请号：SG2012043196

申请日：2004-12-07

Applicant: LAM RES CORP

Inventor： DORDI YEZDI ,  BOYD JOHN ,  THIE WILLIAM ,  MARASCHIN BOB ,  REDEKER FRED C ,  COOK JOEL M

IPC: C23C18/16 ,  C23C18/54

Abstract: OF THE DISCLOSURE A method and an apparatus are provided for selective heating of a surface of a wafer5 exposed to an electroless plating solution. Selective heating by a radiant energy source causes a temperature increase at an interface between the wafer surface and the electroless plating solution. This temperature increase causes a plating reaction to occur at the wafer surface. Thus, material is deposited on the wafer surface through an electroless plating reaction that is initiated and controlled by varying the temperature of the wafer surface using an appropriately10 defined radiant energy source. Additionally, a planar member can be positioned over and proximate to the wafer surface to entrap electroless plating solution between the planar member and the wafer surface. Material deposited through the plating reactions forms a planarizing layer that conforms to a planarity of the planar member.15 Figure 2A

公开(公告)号：IL170851A

公开(公告)日：2010-05-31

申请号：IL17085105

申请日：2005-09-13

Applicant: LAM RES CORP ,  III ANDREW D BAILEY ,  LOHOKARE SHRIKANT P ,  HEMKER DAVID ,  COOK JOEL M

Inventor： III ANDREW D BAILEY ,  LOHOKARE SHRIKANT P ,  HEMKER DAVID ,  COOK JOEL M

IPC: H01L21/3105 ,  H01L21/321 ,  H01L21/3213 ,  H01L21/768

Abstract: A system and method for planarizing a patterned semiconductor substrate includes receiving a patterned semiconductor substrate. The patterned semiconductor substrate having a conductive interconnect material filling multiple of features in the pattern. The conductive interconnect material having an overburden portion. The overburden portion includes a localized non-uniformity. An additional layer is formed on the overburden portion. The additional layer and the overburden portion are planarized. The planarizing process substantially entirely removes the additional layer.