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    SEMICONDUCTOR DEVICE AND MASK FOR SEMICONDUCTOR
    4.
    发明专利
    SEMICONDUCTOR DEVICE AND MASK FOR SEMICONDUCTOR 失效

    公开(公告)号：JPH0437046A

    公开(公告)日：1992-02-07

    申请号：JP14319890

    申请日：1990-05-31

    Applicant: MATSUSHITA ELECTRONICS CORP

    Inventor： TAKAYAMA YUICHIRO ,  TODOKORO YOSHIHIRO ,  INOUE MORIO

    IPC: G01N21/88 ,  G01N21/956 ,  H01L21/66

    Abstract: PURPOSE:To realize periodic arrangement on the whole surface of a semiconductor substrate, by a method wherein the sum of the dimension of a peripheral circuit part containing bonding pads and that of a scribe trench are made equal to integer times a rectangular unit figure. CONSTITUTION:In a region 2, only the rectangular unit regions 1 are arranged in regular order on a chip. The distance in x-direction and the distance in y-direction between the region 2 and a region 3 or a region 4 which are adjacent to the region 2 are set so as to satisfy equations, where xe is the width of a left peripheral circuit in x-direction, xr is the width of a right peripheral circuit region in x-direction, yu is the width of an upper peripheral circuit region in y-direction, yd is the width of a lower peripheral circuit region in y-direction, sx is the width of a scribe trench region in x-direction, sy is the width of a scribe trench region in x-direction, sy is the width of a scribe trench region in y-direction, ux is the width of the unit figure in x-direction, and uy is the width of unit figure in y-derection. In order to satisfy the above relations for the dimensions of the scibe trench 5 and the peripheral circuit part 6, the width sx of the scribe trench in x-direction may be increased or decreased in the distance range of 0-+ or -ux, in response to necessity as far as the x-direction is concerned. As to the y-direction also, the similar process can be applied.

    MANUFACTURE OF MOS TYPE SEMICONDUCTOR DEVICE
    5.
    发明专利
    MANUFACTURE OF MOS TYPE SEMICONDUCTOR DEVICE 失效

    公开(公告)号：JPH02246227A

    公开(公告)日：1990-10-02

    申请号：JP6803589

    申请日：1989-03-20

    Applicant: MATSUSHITA ELECTRONICS CORP

    Inventor： TODOKORO YOSHIHIRO

    IPC: H01L21/336 ,  H01L29/78

    Abstract: PURPOSE:To obtain the overlapped structure of a gate, a source and a drain by forming an n-type low concentration diffused layer, performing anisotropic etching of a thin film which is formed on the entire surface, forming a side wall, expanding the width, and forming an n-type high concentration diffused layer. CONSTITUTION:A gate oxide film 2 is grown on a P-type silicon substrate 1. A polysilicon film 3 is formed thereon. Thereafter, high concentration phosphorus is diffused in a vapor phase, and a low resistance film is formed. With a resist film 6 as a mask, phosphorus ions are implanted with a sufficient accelerating voltage which can penetrate the polysilicon film 3, and an n-type low concentration diffused layer 7 is formed. Then a silicon nitride film 9 is deposited. Fluorine based etching gas is used, and anisotropic dry etching is performed. Then, the silicon nitride film 9 remains on the side wall of the resist film 6. A specified pattern whose width is expanded is obtained. Then, the polysilicon film 3 is removed, and a polysilicon gate 10 is formed. Thereafter, arsenic ions are implanted with an accelerating voltage which can penetrate the gate oxide filmed 2. Thus, an n-type high-concentration diffused layer 8 is formed. In this way, a structure wherein the gate, the source and the drain are overlapped is obtained.

    METHOD FOR DEVELOPING RESIST
    7.
    发明专利
    METHOD FOR DEVELOPING RESIST 失效

    公开(公告)号：JPH01177540A

    公开(公告)日：1989-07-13

    申请号：JP162388

    申请日：1988-01-07

    Applicant: MATSUSHITA ELECTRONICS CORP

    Inventor： WATANABE HISASHI ,  TODOKORO YOSHIHIRO

    IPC: G03F7/00 ,  G03F7/32 ,  H01L21/027 ,  H01L21/30

    Abstract: PURPOSE:To provide the higher sensitivity than in the case of using respective developing soln. alone by mixing >=2 kinds of the developing solns. and developing a resist by such developing soln. mixture. CONSTITUTION:The resist is developed by using the soln. mixture composed of a 1st org. soln. and 2nd org. soln. of respectively satisfying delta1 12.5 where the solubility parameters of the 1st org. soln. and the 2nd soln. are designated and delta1, delta2 in the case of developing the resist consisting of a high polymer of the solubility parameter deltaR. For example, polymethyl methacrylate (PMMA) having 11.3 solubility parameter deltaR is used as the resist, methyl isobutyl ketone (MIBK) having 8.57 solubility parameter delta1 is used as the 1st org. solvent and methyl alcohol (MeOH) having 14.28 solubility parameter delta2 is used as the 2nd org. soln. The higher sensitivity is thereby obtd. in the case of developing the resist by using >=2 kinds of the developing solns. in combination than in the case of using the respective developing solns. alone.

    FORMATION OF TUNGSTEN PATTERN
    8.
    发明专利
    FORMATION OF TUNGSTEN PATTERN 失效

    公开(公告)号：JPS63202037A

    公开(公告)日：1988-08-22

    申请号：JP3386987

    申请日：1987-02-17

    Applicant: MATSUSHITA ELECTRONICS CORP

    Inventor： NIKAWA HIDEO ,  TODOKORO YOSHIHIRO

    IPC: H01L21/3205 ,  H01L21/027 ,  H01L21/30 ,  H01L23/52

    Abstract: PURPOSE:To simplify the manufacturing process and to form a minute tungsten pattern, by applying the tungsten, which is dissolved in hydrogen peroxide water, shrinking the tungsten by heat treatment, and removing a resist film. CONSTITUTION:A resist pattern, which has the width of 0.3 mum for the pattern of an opening part, is formed. Thereafter, 1g of tungsten powder having the purity of 99.999% is dissolved into 5 ml of aqueous hydrogen peroxide. The solution, which is prepared at this rate, is applied at the rotating speed of 1,000 rotations/min, and a tungsten film 7 having the thickness of 0.7 mum is formed. When heat treatment is performed, the applied tungsten film 7 is contracted by 0.2 mum. Then etching is performed, and the tungsten film 7 on electron beam resist 5 and polymethyl methacrylate of the electron beam resist 5 are removed. Thus a minute tungsten pattern having the pattern width of 0.1mum can be obtained. In this way, the manufacturing process is simplified, and the tungsten pattern, which is more minute than the formed resist pattern, can be formed.

    FORMING METHOD FOR CONDUCTING THIN FILM
    10.
    发明专利
    FORMING METHOD FOR CONDUCTING THIN FILM 失效

    公开(公告)号：JPS6257218A

    公开(公告)日：1987-03-12

    申请号：JP19803185

    申请日：1985-09-06

    Applicant: MATSUSHITA ELECTRONICS CORP

    Inventor： TODOKORO YOSHIHIRO ,  TAKASU YASUHIRO ,  OKUMA TORU

    IPC: H01L21/30 ,  H01L21/027

    Abstract: PURPOSE:To prevent a charge-up phenomenon, which is yielded in electron beam exposure in a process including a resin film and resist, by forming an applied film of an organic metal solution including In and Sn together wth a resin film on a substrate, and performing heat treatment at a low temperature. CONSTITUTION:On a quartz substrate 1, photoresist (manufactured by Tokyo Oka Co.; trade name, OFPR800) is applied to a thickness of 2mum. Heat treatment is performed at 280 deg.C for 30min. On said resist, an organic metal solution (manu factured by Tokyo Oka Co.; trade name, TCG), which includes In and Sn at a constituting ratio of Sn/In of 0.02-0.2, was applied to a thickness of about 800Angstrom . Heat treatment was performed at 280 deg.C for 30min. Thus an ITO film 4 was formed. Thereafter, electron beam exposure was performed. At this time, in the experiment, no charge-up occurred on the insulating substrate at all.

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