公开(公告)号：JPH11316679A

公开(公告)日：1999-11-16

申请号：JP30756198

申请日：1998-10-28

Applicant: MICROCHIP TECH INC

Inventor： WOJEWODA IGOR ,  DRAKE RODNEY J ,  MITRA SUMIT

IPC: G06F9/34 ,  G06F9/30 ,  G06F9/35 ,  G06F12/06

Abstract: PROBLEM TO BE SOLVED: To encode many addressing modes and also to have many bank address value generation sources by preparing a data memory having plural data banks, a selection circuit which selects one of bank address value generation sources, a bank selection register and an instruction register. SOLUTION: A data memory 12 is connected to a CPU to store and transfer data. One of plural banks of the memory 12 serves as a general-purpose/special register. A selection circuit 14 selects one of many bank address value generation sources. A bank selection register 18 supplies a bank address value for an instruction that is executed in a direct short addressing mode. An instruction register 22 supplies a bank address value for an instruction that is executed in a direct long addressing mode and also supplies a bank address value for an instruction that is executed in a direct short addressing mode.

公开(公告)号：JPH11212787A

公开(公告)日：1999-08-06

申请号：JP30613498

申请日：1998-10-27

Applicant: MICROCHIP TECH INC

Inventor： MITRA SUMIT ,  TRIECE JOSEPH W

IPC: G06F9/30 ,  G06F9/318 ,  G06F9/34 ,  G06F9/35 ,  G06F9/355

Abstract: PROBLEM TO BE SOLVED: To maximize the number of usable operation codes and addressable registers and also to enable a multiple addressing mode by having an instruction set which can realize an addressing mode in which plural instructions are different from each other. SOLUTION: An instruction 30 includes plural bits 32. The bits 32 are divided into an operation code field 34 that shows what type of an operation is performed, a destination bit 36 that shows where operation results are stored and a register address field 38 which shows a register where the instruction 30 is operated or the address of variable data. The lengths of the fields 34 and 38 are determined by the number of operation codes a user desires to realize or the number of addressable registers. Virtual register address positions in a processor architecture system used together with the instruction 30 respectively start an indirect addressing mode when they are accessed.

公开(公告)号：DE69230642D1

公开(公告)日：2000-03-09

申请号：DE69230642

申请日：1992-11-12

Applicant: MICROCHIP TECH INC

Inventor： CHEN CHAO-WU ,  ROSENHAGEN KURT ,  ITALIANO GREG ,  MITRA SUMIT

IPC: G06F9/24 ,  G06F9/445 ,  G06F9/06 ,  G06F12/02

Abstract: A microcontroller fabricated on a semiconductor chip is adapted, when operating, to execute programs and instructions and, in response, to generate control signals to selectively control external apparatus. A clock generates timing signals to control the timing of the microcontroller execution and operation. An on-chip program memory has space avilable for storing a program to be executed by the microcontroller in sequential steps in successive address locations of the program memory. An instruction stored in unerasable memory on the chip initiates self-programming of the program memory with the program to be executed by the microcontroller by enabling a pointer timed by the clock to alternately read addresses containing steps of the program to be executed from off-chip memories and to write same into successive addresses of the on-chip program memory by incrementing the latter addresses with each step to be written therein.

公开(公告)号：DE69231230D1

公开(公告)日：2000-08-10

申请号：DE69231230

申请日：1992-11-12

Applicant: MICROCHIP TECH INC

Inventor： YACH RANDY L ,  MITRA SUMIT

IPC: G06F1/04 ,  G06F1/24 ,  G06F11/267 ,  G06F15/78 ,  G06F11/00 ,  G06F1/00 ,  G06F9/00 ,  H03K17/22 ,  H03K17/28

Abstract: A microcontroller is adapted, when operating, to execute programs and instructions and, in response, to generate control signals to selectively control external apparatus. The microcontroller includes a power supply for supplying power to the overall device within a predetermined range suitable for its operation, and a clock for supplying a clock frequency to the microcontroller with a stability suitable for precise timing and counting within the device. The microcontroller is selectively reset to prevent it from executing programs and instructions for purposes of generating the control signals, and is maintained in the reset condition despite initiation of a removal from the reset condition, until the power supplied by the power supply is in a predetermined range and the clock frequency supplied by the clock is stable. In this way, no execution by the microcontroller is permitted until device stability is achieved, to prevent errors in execution. In the disclosed embodiment, the reset condition is maintained by a power-up timer and an oscillator start-up timer, each timer having a programmable timeout interval to end the reset condition only when the timeout intervals of both timers have expired.

公开(公告)号：DE69231230T2

公开(公告)日：2001-03-01

申请号：DE69231230

申请日：1992-11-12

Applicant: MICROCHIP TECH INC

Inventor： YACH RANDY L ,  MITRA SUMIT

IPC: G06F1/04 ,  G06F1/24 ,  G06F11/267 ,  G06F15/78 ,  G06F11/00 ,  G06F1/00 ,  G06F9/00 ,  H03K17/22 ,  H03K17/28

Abstract: A microcontroller is adapted, when operating, to execute programs and instructions and, in response, to generate control signals to selectively control external apparatus. The microcontroller includes a power supply for supplying power to the overall device within a predetermined range suitable for its operation, and a clock for supplying a clock frequency to the microcontroller with a stability suitable for precise timing and counting within the device. The microcontroller is selectively reset to prevent it from executing programs and instructions for purposes of generating the control signals, and is maintained in the reset condition despite initiation of a removal from the reset condition, until the power supplied by the power supply is in a predetermined range and the clock frequency supplied by the clock is stable. In this way, no execution by the microcontroller is permitted until device stability is achieved, to prevent errors in execution. In the disclosed embodiment, the reset condition is maintained by a power-up timer and an oscillator start-up timer, each timer having a programmable timeout interval to end the reset condition only when the timeout intervals of both timers have expired.

公开(公告)号：AT522860T

公开(公告)日：2011-09-15

申请号：AT00915025

申请日：2000-03-23

Applicant: MICROCHIP TECH INC

Inventor： BOLES EDWARD ,  DRAKE RODNEY ,  JOHANSEN DARREL ,  MITRA SUMIT ,  TRIECE JOSEPH ,  YACH RANDY

IPC: G06F9/30 ,  G06F9/312 ,  G06F9/315 ,  G06F9/318 ,  G06F9/32 ,  G06F9/34 ,  G06F9/35 ,  G06F12/00

Abstract: A microcontroller apparatus is provided with an instruction set for manipulating the behavior of the microcontroller. The apparatus and system is provided that enables a linearized address space that makes modular emulation possible. Direct or indirect addressing is possible through register files or data memory. Special function registers, including the Program Counter (PC) and Working Register (W), are mapped in the data memory. An orthogonal (symmetrical) instruction set makes possible any operation on any register using any addressing mode. Consequently, two file registers to be used in some two operand instructions. This allows data to be moved directly between two registers without going through the W register. Thus increasing performance and decreasing program memory usage.

公开(公告)号：AT435526T

公开(公告)日：2009-07-15

申请号：AT06720998

申请日：2006-02-21

Applicant: MICROCHIP TECH INC

Inventor： MITRA SUMIT ,  HU HARRY ,  SCHIEKE PIETER

IPC: H03M1/46 ,  H03M1/68 ,  H03M1/80

公开(公告)号：DE69230642T2

公开(公告)日：2001-05-23

申请号：DE69230642

申请日：1992-11-12

Applicant: MICROCHIP TECH INC

Inventor： CHEN CHAO-WU ,  ROSENHAGEN KURT ,  ITALIANO GREG ,  MITRA SUMIT

IPC: G06F9/24 ,  G06F9/445 ,  G06F9/06 ,  G06F12/02

Abstract: A microcontroller fabricated on a semiconductor chip is adapted, when operating, to execute programs and instructions and, in response, to generate control signals to selectively control external apparatus. A clock generates timing signals to control the timing of the microcontroller execution and operation. An on-chip program memory has space avilable for storing a program to be executed by the microcontroller in sequential steps in successive address locations of the program memory. An instruction stored in unerasable memory on the chip initiates self-programming of the program memory with the program to be executed by the microcontroller by enabling a pointer timed by the clock to alternately read addresses containing steps of the program to be executed from off-chip memories and to write same into successive addresses of the on-chip program memory by incrementing the latter addresses with each step to be written therein.

公开(公告)号：WO2004095364A8

公开(公告)日：2005-10-20

申请号：PCT/US2004012134

申请日：2004-04-20

Applicant: MICROCHIP TECH INC ,  BOLES BRIAN ,  FISCHER RICHARD ,  MITRA SUMIT ,  DRAKE RODNEY ,  BOWLING STEVEN A ,  KRIS BRYAN ,  MARSH STEVEN ,  HARB HASSAN

Inventor： BOLES BRIAN ,  FISCHER RICHARD ,  MITRA SUMIT ,  DRAKE RODNEY ,  BOWLING STEVEN A ,  KRIS BRYAN ,  MARSH STEVEN ,  HARB HASSAN

IPC: G06F15/76 ,  G06F17/50

CPC classification number: G06F17/5068 ,  G06F15/76

公开(公告)号：EP0614550A4

公开(公告)日：1994-07-18

申请号：EP92925068

申请日：1992-11-12

Applicant: MICROCHIP TECH INC

Inventor： CHEN CHAO-WU ,  ROSENHAGEN KURT ,  ITALIANO GREG ,  MITRA SUMIT

IPC: G06F9/24 ,  G06F9/445 ,  G06F9/06 ,  G06F12/02

CPC classification number: G06F9/24 ,  G06F9/445

Abstract: A microcontroller (10) fabricated on a semiconductor chip is adapted, when operating, to execute programs (17) and instructions and, in response, to generate control signals to selectively control external apparatus. A clock (15) generates timing signals to control the timing of the microcontroller execution and operation. An on-chip program memory (17) has space available for storing a program to be executed by the microcontroller in sequential steps in successive address locations of the program memory. An instruction stored in unerasable memory on the chip initiates self-programming of the program memory with the program to be executed by the microcontroller by enabling a pointer timed by the clock to alternately read addresses containing steps of the program to be executed from off-chip memories and to write same into successive addresses of the on-chip program memory by incrementing the latter addresses with each step to be written therein.