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    PROCEDE DE FORMATION DE VIAS ELECTRIQUES
    2.
    发明专利
    PROCEDE DE FORMATION DE VIAS ELECTRIQUES 未知

    公开(公告)号：FR2958076A1

    公开(公告)日：2011-09-30

    申请号：FR1052110

    申请日：2010-03-24

    Applicant: ST MICROELECTRONICS SA ,  ST MICROELECTRONICS CROLLES 2

    Inventor： FOURNEL RICHARD ,  DODO YVES

    IPC: H01L21/768

    Abstract: L'invention concerne un procédé de formation de vias traversants (14) reliant la face avant à la face arrière d'un substrat semiconducteur (1), comprenant les étapes suivantes : a) former des ouvertures dans le substrat, b) oxyder thermiquement des parois des ouvertures, c) remplir les ouvertures d'un matériau sacrificiel, d) réaliser des composants électroniques (T1, T2) dans le substrat, e) graver le matériau sacrificiel, f) remplir les ouvertures d'un métal, g) graver la face arrière du substrat jusqu'au niveau du fond des ouvertures.

    MEMORY DEVICE AND INTEGRATED CIRCUIT
    6.
    发明专利
    MEMORY DEVICE AND INTEGRATED CIRCUIT 审中-公开

    公开(公告)号：JP2003152119A

    公开(公告)日：2003-05-23

    申请号：JP2002252983

    申请日：2002-08-30

    Applicant: ST MICROELECTRONICS SA

    Inventor： DRAY CYRILLE ,  CASPAR DANIEL ,  FOURNEL RICHARD

    IPC: G11C16/02 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792

    Abstract: PROBLEM TO BE SOLVED: To provide an FAMOS memory location which can have at least three completely natural program levels. SOLUTION: An FAMOS memory location is provided with a single floating gate (GR) overlapping the active plane of a semiconductor substrate along contour (PF1, PF2) of at least two asymmetric overlaps in order to determine at least two electrodes in an active region. A memory location program means (MC, SW) applies a set of specified different voltages selectively to the electrodes such that at least three program logical levels are outputted to the memory location.

    METHOD AND DEVICE FOR REFRESHING REFERENCE CELL
    7.
    发明专利
    METHOD AND DEVICE FOR REFRESHING REFERENCE CELL 审中-公开

    公开(公告)号：JP2002334589A

    公开(公告)日：2002-11-22

    申请号：JP2002026723

    申请日：2002-02-04

    Applicant: ST MICROELECTRONICS SA

    Inventor： FOURNEL RICHARD ,  AITOUARAB LEILA SEDJAI

    IPC: G01R31/28 ,  G11C16/02 ,  G11C16/04 ,  G11C16/06 ,  G11C16/34 ,  G11C29/12 ,  G11C29/00

    Abstract: PROBLEM TO BE SOLVED: To prevent a read error caused by variation of a property of a reference memory cell. SOLUTION: This method is a method for refreshing a reference memory cell (Cref) in a non-volatile memory. This method has a step in which the reference cell (Cref) and a test cell (Cveri) are simultaneously selected during read, read signals are compared when a signal read by the reference cell is smaller than a signal read by the test cell, and refresh signals (Sr1, Sr2, Sr3) are outputted to the reference cell (Cref). This method is applied to an electronic memory of a non-volatile type.

    Non-volatile programmable and electrically erasable memory with single layer of grid material
    8.
    发明专利
    Non-volatile programmable and electrically erasable memory with single layer of grid material 审中-公开
    具有单层网格材料的非易失性可编程和电可擦除存储器

    公开(公告)号：JP2003273257A

    公开(公告)日：2003-09-26

    申请号：JP2003057906

    申请日：2003-03-05

    Applicant: St Microelectronics Sa ,  エスティマイクロエレクトロニクス エスエー

    Inventor： DRAY CYRILLE ,  GENDRIER PHILIPPE ,  FOURNEL RICHARD

    IPC: H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

    CPC classification number: H01L27/11521 ,  H01L27/115 ,  H01L27/11558 ,  H01L29/66825 ,  H01L29/7883

    Abstract: PROBLEM TO BE SOLVED: To provide a memory device which overcomes the data holding problem caused by the thinness of its grid dielectric present in the interface between its STI-type isolation region and its grid material.
    SOLUTION: The semiconductor memory device comprises a non-volatile programmable and electrically erasable memory cell having a single layer of grid material. Also, the memory cell comprises a floating grid transistor and a control grid within an active semiconductor area which is formed in a region of a substrate and is delimited by an isolation region. The single layer of grid material wherein the floating grid is formed extends integrally above the active semiconductor area without overlapping part of the isolation region. The floating grid transistor is electrically isolated from the control grid by PN junctions that are inversely polarized.
    COPYRIGHT: (C)2003,JPO

    Abstract translation: 要解决的问题：提供一种克服由其STI型隔离区域和其栅格材料之间的界面中存在的栅极电介质薄度引起的数据保持问题的存储器件。 解决方案：半导体存储器件包括具有单层栅格材料的非易失性可编程和电可擦除存储单元。 此外，存储单元包括浮动栅极晶体管和在有源半导体区域内的控制栅格，该有源半导体区域形成在衬底的区域中并由隔离区域限定。 其中形成浮栅的单层栅格材料在有源半导体区域上整体地延伸，而不与隔离区的重叠部分重叠。 浮栅晶体管通过PN极点与控制栅极电隔离，反向极化。 版权所有（C）2003，JPO

    INTEGRATED CIRCUIT WITH BUILT-IN PROTECTIVE RELAY
    10.
    发明专利
    INTEGRATED CIRCUIT WITH BUILT-IN PROTECTIVE RELAY 审中-公开

    公开(公告)号：JP2002135970A

    公开(公告)日：2002-05-10

    申请号：JP2001201430

    申请日：2001-07-02

    Applicant: ST MICROELECTRONICS SA

    Inventor： FOURNEL RICHARD

    IPC: H02H7/20 ,  G09C1/00 ,  H03K17/10 ,  H03K17/693 ,  H04L9/10

    Abstract: PROBLEM TO BE SOLVED: To prevent access to confidential information. SOLUTION: This integrated circuit has a reference ground voltage Gnd and a power supply voltage Vdd for logical operation and is applied with a high voltage HV. It has a protective device 2 that has, at least, one gate oxide circuit element in combination. The protective device 2 is applied with a logical operation voltage Vdd at the power supply node N of, at least, one of the gate oxide circuit elements when operating normally, but the high voltage VH is applied to break down the gate oxide when malfunctioning.

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