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    1.
    发明专利
    未知

    公开(公告)号：DE602005004253D1

    公开(公告)日：2008-02-21

    申请号：DE602005004253

    申请日：2005-01-28

    Applicant: ST MICROELECTRONICS SRL

    Inventor： SFORZIN MARCO ,  DEL GATTO NICOLA ,  FERRARIO MARCO ,  CONFALONIERI EMANUELE

    IPC: G11C16/26 ,  G11C11/56

    Abstract: A memory device (100) is proposed. The memory device includes a plurality of memory cells (Mc) each one for storing a value, at least one reference cell (Mr 0 -Mr 2 ), biasing means (115) for biasing a set of selected memory cells and the at least one reference cell with a biasing voltage (Vc,Vr) having a substantially monotone time pattern, means (130) for detecting the reaching of a threshold value by a current (Ic,Ir) of each selected memory cell and of each reference cell, and means (145) for determining the value stored in each selected memory cell according to a temporal relation of the reaching of the threshold value by the currents of the selected memory cell and of the at least one reference cell. The biasing means includes means (305) for applying a predetermined biasing current (Ib) to the selected memory cells and to the at least one reference cell.

    2.
    发明专利
    未知

    公开(公告)号：ITTO20010530A1

    公开(公告)日：2002-12-02

    申请号：ITTO20010530

    申请日：2001-06-01

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CONFALONIERI EMANUELE ,  GERACI ANTONIO ,  SFORZIN MARCO ,  BEDARIDA LORENZO

    IPC: G11C7/10

    Abstract: Described herein is an output buffer including an output stage formed by a pull-up transistor and a pull-down transistor, which are connected in series between a supply line set at a supply potential and a ground line set at a ground potential, with an intermediate node connected to the output of the output buffer. The output buffer further includes a unidirectional decoupling stage arranged between the output of the output buffer and the pull-up transistor for decoupling the output from the supply line during the switching transients of the output buffer in such a way as to prevent the switching noise present on the latter from being transferred onto the output of the output buffer.

    5.
    发明专利
    未知

    公开(公告)号：ITTO20010530D0

    公开(公告)日：2001-06-01

    申请号：ITTO20010530

    申请日：2001-06-01

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CONFALONIERI EMANUELE ,  GERACI ANTONIO ,  SFORZIN MARCO ,  BEDARIDA LORENZO

    IPC: G11C7/10

    Abstract: Described herein is an output buffer including an output stage formed by a pull-up transistor and a pull-down transistor, which are connected in series between a supply line set at a supply potential and a ground line set at a ground potential, with an intermediate node connected to the output of the output buffer. The output buffer further includes a unidirectional decoupling stage arranged between the output of the output buffer and the pull-up transistor for decoupling the output from the supply line during the switching transients of the output buffer in such a way as to prevent the switching noise present on the latter from being transferred onto the output of the output buffer.

    7.
    发明专利
    未知

    公开(公告)号：DE602005004253T2

    公开(公告)日：2009-01-08

    申请号：DE602005004253

    申请日：2005-01-28

    Applicant: ST MICROELECTRONICS SRL

    Inventor： SFORZIN MARCO ,  DEL GATTO NICOLA ,  FERRARIO MARCO ,  CONFALONIERI EMANUELE

    IPC: G11C16/26 ,  G11C11/56

    Abstract: A memory device (100) is proposed. The memory device includes a plurality of memory cells (Mc) each one for storing a value, at least one reference cell (Mr 0 -Mr 2 ), biasing means (115) for biasing a set of selected memory cells and the at least one reference cell with a biasing voltage (Vc,Vr) having a substantially monotone time pattern, means (130) for detecting the reaching of a threshold value by a current (Ic,Ir) of each selected memory cell and of each reference cell, and means (145) for determining the value stored in each selected memory cell according to a temporal relation of the reaching of the threshold value by the currents of the selected memory cell and of the at least one reference cell. The biasing means includes means (305) for applying a predetermined biasing current (Ib) to the selected memory cells and to the at least one reference cell.

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