公开(公告)号：DE602005004253T2

公开(公告)日：2009-01-08

申请号：DE602005004253

申请日：2005-01-28

Applicant: ST MICROELECTRONICS SRL

Inventor： SFORZIN MARCO ,  DEL GATTO NICOLA ,  FERRARIO MARCO ,  CONFALONIERI EMANUELE

IPC: G11C16/26 ,  G11C11/56

Abstract: A memory device (100) is proposed. The memory device includes a plurality of memory cells (Mc) each one for storing a value, at least one reference cell (Mr 0 -Mr 2 ), biasing means (115) for biasing a set of selected memory cells and the at least one reference cell with a biasing voltage (Vc,Vr) having a substantially monotone time pattern, means (130) for detecting the reaching of a threshold value by a current (Ic,Ir) of each selected memory cell and of each reference cell, and means (145) for determining the value stored in each selected memory cell according to a temporal relation of the reaching of the threshold value by the currents of the selected memory cell and of the at least one reference cell. The biasing means includes means (305) for applying a predetermined biasing current (Ib) to the selected memory cells and to the at least one reference cell.

公开(公告)号：ITMI20041957A1

公开(公告)日：2005-01-15

申请号：ITMI20041957

申请日：2004-10-15

Applicant: ST MICROELECTRONICS SRL

Inventor： CONFALONIERI EMANUELE ,  DEL GATTO NICOLA ,  POIDOMANI CARLA GIUSEPPINA ,  SFORZIN MARCO

公开(公告)号：ITVA20050007A1

公开(公告)日：2006-08-09

申请号：ITVA20050007

申请日：2005-02-08

Applicant: ST MICROELECTRONICS SRL

Inventor： DEL GATTO NICOLA ,  GERACI ANTONIO ,  ROSITO NICOLA ,  SFORZIN MARCO

公开(公告)号：ITTO20010530D0

公开(公告)日：2001-06-01

申请号：ITTO20010530

申请日：2001-06-01

Applicant: ST MICROELECTRONICS SRL

Inventor： CONFALONIERI EMANUELE ,  GERACI ANTONIO ,  SFORZIN MARCO ,  BEDARIDA LORENZO

IPC: G11C7/10

Abstract: Described herein is an output buffer including an output stage formed by a pull-up transistor and a pull-down transistor, which are connected in series between a supply line set at a supply potential and a ground line set at a ground potential, with an intermediate node connected to the output of the output buffer. The output buffer further includes a unidirectional decoupling stage arranged between the output of the output buffer and the pull-up transistor for decoupling the output from the supply line during the switching transients of the output buffer in such a way as to prevent the switching noise present on the latter from being transferred onto the output of the output buffer.

公开(公告)号：DE60041056D1

公开(公告)日：2009-01-22

申请号：DE60041056

申请日：2000-08-16

Applicant: ST MICROELECTRONICS SRL

Inventor： GERACI ANTONINO ,  LISI CARLO ,  BEDARIDA LORENZO ,  SFORZIN MARCO

IPC: G11C16/28 ,  G11C7/12

Abstract: A direct-comparison reading circuit for a nonvolatile memory array (2) having a plurality of memory cells (4) arranged in rows and columns (9), and at least one bit line (7), includes at least one array line (13), selectively connectable to the bit line (7), and a reference line (14); a precharging circuit (17) for precharging the array line (13) and reference line (14) at a preset precharging potential (VPC); at least one comparator (35) having a first terminal connected to the array line (13), and a second terminal connected to the reference line (14); and an equalization circuit (15, 23, 26) for equalizing the potentials of the array line (13) and reference line (14) in the precharging step. In addition, the reading circuit includes an equalization line (15) distinct from the reference line (14); and controlled switches (23, 26) for connecting, in the precharging step, the equalization line (15) to the array line (13) and to the reference line (14), and for disconnecting the equalization line (15) from the array line (13) and from the reference line (14) at the end of the precharging step.

公开(公告)号：DE602005004253D1

公开(公告)日：2008-02-21

申请号：DE602005004253

申请日：2005-01-28

Applicant: ST MICROELECTRONICS SRL

Inventor： SFORZIN MARCO ,  DEL GATTO NICOLA ,  FERRARIO MARCO ,  CONFALONIERI EMANUELE

IPC: G11C16/26 ,  G11C11/56

Abstract: A memory device (100) is proposed. The memory device includes a plurality of memory cells (Mc) each one for storing a value, at least one reference cell (Mr 0 -Mr 2 ), biasing means (115) for biasing a set of selected memory cells and the at least one reference cell with a biasing voltage (Vc,Vr) having a substantially monotone time pattern, means (130) for detecting the reaching of a threshold value by a current (Ic,Ir) of each selected memory cell and of each reference cell, and means (145) for determining the value stored in each selected memory cell according to a temporal relation of the reaching of the threshold value by the currents of the selected memory cell and of the at least one reference cell. The biasing means includes means (305) for applying a predetermined biasing current (Ib) to the selected memory cells and to the at least one reference cell.

公开(公告)号：ITTO20010530A1

公开(公告)日：2002-12-02

申请号：ITTO20010530

申请日：2001-06-01

Applicant: ST MICROELECTRONICS SRL

Inventor： CONFALONIERI EMANUELE ,  GERACI ANTONIO ,  SFORZIN MARCO ,  BEDARIDA LORENZO

IPC: G11C7/10

Abstract: Described herein is an output buffer including an output stage formed by a pull-up transistor and a pull-down transistor, which are connected in series between a supply line set at a supply potential and a ground line set at a ground potential, with an intermediate node connected to the output of the output buffer. The output buffer further includes a unidirectional decoupling stage arranged between the output of the output buffer and the pull-up transistor for decoupling the output from the supply line during the switching transients of the output buffer in such a way as to prevent the switching noise present on the latter from being transferred onto the output of the output buffer.

公开(公告)号：DE602004012271T2

公开(公告)日：2009-03-19

申请号：DE602004012271

申请日：2004-10-08

Applicant: ST MICROELECTRONICS SRL

Inventor： SFORZIN MARCO ,  DEL GATTO NICOLA ,  MOLLICHELLI MASSIMILIANO ,  SCOTTI MASSIMILIANO

IPC: G11C16/24

Abstract: In a memory device (1; 30) having an array (2) of memory cells (3), a column decoder (9) is configured to address the memory cells (3), and a charge-pump supply circuit (6; 32) generates a boosted supply voltage (V b ; V yr ) for the column decoder (9). A connecting stage (22) is arranged between the supply circuit (6; 32) and the column decoder (9); the connecting stage (22) switches between a high-impedance state and a low-impedance state, and is configured to switch into the high-impedance state in given operating conditions of the memory device (1; 30), in particular during a reading step.

公开(公告)号：DE602004012271D1

公开(公告)日：2008-04-17

申请号：DE602004012271

申请日：2004-10-08

Applicant: ST MICROELECTRONICS SRL

Inventor： SFORZIN MARCO ,  DEL GATTO NICOLA ,  MOLLICHELLI MASSIMILIANO ,  SCOTTI MASSIMILIANO

IPC: G11C16/24

Abstract: In a memory device (1; 30) having an array (2) of memory cells (3), a column decoder (9) is configured to address the memory cells (3), and a charge-pump supply circuit (6; 32) generates a boosted supply voltage (V b ; V yr ) for the column decoder (9). A connecting stage (22) is arranged between the supply circuit (6; 32) and the column decoder (9); the connecting stage (22) switches between a high-impedance state and a low-impedance state, and is configured to switch into the high-impedance state in given operating conditions of the memory device (1; 30), in particular during a reading step.

公开(公告)号：ITMI20012817A1

公开(公告)日：2003-06-30

申请号：ITMI20012817

申请日：2001-12-28

Applicant: ST MICROELECTRONICS SRL

Inventor： CONFALONIERI EMANUELE ,  SFORZIN MARCO

IPC: G06F11/10 ,  G06F12/00 ,  G11C8/00

Abstract: A decoding structure for a memory device with a control code is used in a memory including a matrix of memory cells grouped into pages to each of which a block of control information is associated, and a plurality of reading elements for reading a plurality of pages in parallel. The decoding structure selectively connects each reading element to a plurality of memory cells, and selectively connects each memory cell to a plurality of reading elements.