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6 records (took 0.021 seconds)

    1.
    发明专利
    未知

    公开(公告)号：DE602005004253D1

    公开(公告)日：2008-02-21

    申请号：DE602005004253

    申请日：2005-01-28

    Applicant: ST MICROELECTRONICS SRL

    Inventor： SFORZIN MARCO ,  DEL GATTO NICOLA ,  FERRARIO MARCO ,  CONFALONIERI EMANUELE

    IPC: G11C16/26 ,  G11C11/56

    Abstract: A memory device (100) is proposed. The memory device includes a plurality of memory cells (Mc) each one for storing a value, at least one reference cell (Mr 0 -Mr 2 ), biasing means (115) for biasing a set of selected memory cells and the at least one reference cell with a biasing voltage (Vc,Vr) having a substantially monotone time pattern, means (130) for detecting the reaching of a threshold value by a current (Ic,Ir) of each selected memory cell and of each reference cell, and means (145) for determining the value stored in each selected memory cell according to a temporal relation of the reaching of the threshold value by the currents of the selected memory cell and of the at least one reference cell. The biasing means includes means (305) for applying a predetermined biasing current (Ib) to the selected memory cells and to the at least one reference cell.

    4.
    发明专利
    未知

    公开(公告)号：DE602005004253T2

    公开(公告)日：2009-01-08

    申请号：DE602005004253

    申请日：2005-01-28

    Applicant: ST MICROELECTRONICS SRL

    Inventor： SFORZIN MARCO ,  DEL GATTO NICOLA ,  FERRARIO MARCO ,  CONFALONIERI EMANUELE

    IPC: G11C16/26 ,  G11C11/56

    Abstract: A memory device (100) is proposed. The memory device includes a plurality of memory cells (Mc) each one for storing a value, at least one reference cell (Mr 0 -Mr 2 ), biasing means (115) for biasing a set of selected memory cells and the at least one reference cell with a biasing voltage (Vc,Vr) having a substantially monotone time pattern, means (130) for detecting the reaching of a threshold value by a current (Ic,Ir) of each selected memory cell and of each reference cell, and means (145) for determining the value stored in each selected memory cell according to a temporal relation of the reaching of the threshold value by the currents of the selected memory cell and of the at least one reference cell. The biasing means includes means (305) for applying a predetermined biasing current (Ib) to the selected memory cells and to the at least one reference cell.

    5.
    发明专利
    未知

    公开(公告)号：DE102007051192A1

    公开(公告)日：2008-06-05

    申请号：DE102007051192

    申请日：2007-10-25

    Applicant: ST MICROELECTRONICS SRL

    Inventor： MAGNAVACCA ALESSANDRO ,  SCOTTI MASSIMILIANO ,  DEL GATTO NICOLA ,  NAVA CLAUDIO ,  FERRARIO MARCO ,  MOLLICHELLI MASSIMILIANO

    IPC: G11C16/06

    Abstract: A memory device may include an array of addressable three-level cells, a coding circuit being input with three-bit strings and generating corresponding ternary strings based upon a code, and a program circuit being input with the ternary strings and storing them in respective pairs of three-level cells. The memory device also may include a read circuit reading stored ternary strings in the respective pairs of three-level cells, and a decoding circuit being input with the stored ternary strings and generating corresponding strings of three bits based upon the code.

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