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    1.
    发明专利
    未知

    公开(公告)号：DE602005004253T2

    公开(公告)日：2009-01-08

    申请号：DE602005004253

    申请日：2005-01-28

    Applicant: ST MICROELECTRONICS SRL

    Inventor： SFORZIN MARCO ,  DEL GATTO NICOLA ,  FERRARIO MARCO ,  CONFALONIERI EMANUELE

    IPC: G11C16/26 ,  G11C11/56

    Abstract: A memory device (100) is proposed. The memory device includes a plurality of memory cells (Mc) each one for storing a value, at least one reference cell (Mr 0 -Mr 2 ), biasing means (115) for biasing a set of selected memory cells and the at least one reference cell with a biasing voltage (Vc,Vr) having a substantially monotone time pattern, means (130) for detecting the reaching of a threshold value by a current (Ic,Ir) of each selected memory cell and of each reference cell, and means (145) for determining the value stored in each selected memory cell according to a temporal relation of the reaching of the threshold value by the currents of the selected memory cell and of the at least one reference cell. The biasing means includes means (305) for applying a predetermined biasing current (Ib) to the selected memory cells and to the at least one reference cell.

    2.
    发明专利
    未知

    公开(公告)号：DE102007051192A1

    公开(公告)日：2008-06-05

    申请号：DE102007051192

    申请日：2007-10-25

    Applicant: ST MICROELECTRONICS SRL

    Inventor： MAGNAVACCA ALESSANDRO ,  SCOTTI MASSIMILIANO ,  DEL GATTO NICOLA ,  NAVA CLAUDIO ,  FERRARIO MARCO ,  MOLLICHELLI MASSIMILIANO

    IPC: G11C16/06

    Abstract: A memory device may include an array of addressable three-level cells, a coding circuit being input with three-bit strings and generating corresponding ternary strings based upon a code, and a program circuit being input with the ternary strings and storing them in respective pairs of three-level cells. The memory device also may include a read circuit reading stored ternary strings in the respective pairs of three-level cells, and a decoding circuit being input with the stored ternary strings and generating corresponding strings of three bits based upon the code.

    4.
    发明专利
    未知

    公开(公告)号：DE602005004253D1

    公开(公告)日：2008-02-21

    申请号：DE602005004253

    申请日：2005-01-28

    Applicant: ST MICROELECTRONICS SRL

    Inventor： SFORZIN MARCO ,  DEL GATTO NICOLA ,  FERRARIO MARCO ,  CONFALONIERI EMANUELE

    IPC: G11C16/26 ,  G11C11/56

    Abstract: A memory device (100) is proposed. The memory device includes a plurality of memory cells (Mc) each one for storing a value, at least one reference cell (Mr 0 -Mr 2 ), biasing means (115) for biasing a set of selected memory cells and the at least one reference cell with a biasing voltage (Vc,Vr) having a substantially monotone time pattern, means (130) for detecting the reaching of a threshold value by a current (Ic,Ir) of each selected memory cell and of each reference cell, and means (145) for determining the value stored in each selected memory cell according to a temporal relation of the reaching of the threshold value by the currents of the selected memory cell and of the at least one reference cell. The biasing means includes means (305) for applying a predetermined biasing current (Ib) to the selected memory cells and to the at least one reference cell.

    5.
    发明专利
    未知

    公开(公告)号：ITTO20020566D0

    公开(公告)日：2002-06-28

    申请号：ITTO20020566

    申请日：2002-06-28

    Applicant: ST MICROELECTRONICS SRL

    Inventor： DEL GATTO NICOLA ,  DIMA VINCENZO ,  POIDOMANI CARLA ,  CHIAVETTA CARMELO

    IPC: G05F3/24 ,  G05F3/26

    Abstract: A voltage regulator with quick response includes: an output terminal supplying a regulated voltage; and at least a first boost circuit, controlled for alternately accumulating a first charge in a first operating condition and supplying the first charge to the output terminal in a second operating condition. In addition, the first boost circuit is provided with a compensation stage supplying the output terminal with a second charge substantially equal to the first charge, when the first boost circuit is in the first operating condition.

    8.
    发明专利
    未知

    公开(公告)号：DE602004012271T2

    公开(公告)日：2009-03-19

    申请号：DE602004012271

    申请日：2004-10-08

    Applicant: ST MICROELECTRONICS SRL

    Inventor： SFORZIN MARCO ,  DEL GATTO NICOLA ,  MOLLICHELLI MASSIMILIANO ,  SCOTTI MASSIMILIANO

    IPC: G11C16/24

    Abstract: In a memory device (1; 30) having an array (2) of memory cells (3), a column decoder (9) is configured to address the memory cells (3), and a charge-pump supply circuit (6; 32) generates a boosted supply voltage (V b ; V yr ) for the column decoder (9). A connecting stage (22) is arranged between the supply circuit (6; 32) and the column decoder (9); the connecting stage (22) switches between a high-impedance state and a low-impedance state, and is configured to switch into the high-impedance state in given operating conditions of the memory device (1; 30), in particular during a reading step.

    9.
    发明专利
    未知

    公开(公告)号：DE602004012271D1

    公开(公告)日：2008-04-17

    申请号：DE602004012271

    申请日：2004-10-08

    Applicant: ST MICROELECTRONICS SRL

    Inventor： SFORZIN MARCO ,  DEL GATTO NICOLA ,  MOLLICHELLI MASSIMILIANO ,  SCOTTI MASSIMILIANO

    IPC: G11C16/24

    Abstract: In a memory device (1; 30) having an array (2) of memory cells (3), a column decoder (9) is configured to address the memory cells (3), and a charge-pump supply circuit (6; 32) generates a boosted supply voltage (V b ; V yr ) for the column decoder (9). A connecting stage (22) is arranged between the supply circuit (6; 32) and the column decoder (9); the connecting stage (22) switches between a high-impedance state and a low-impedance state, and is configured to switch into the high-impedance state in given operating conditions of the memory device (1; 30), in particular during a reading step.

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