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    1.
    发明专利
    未知

    公开(公告)号：IT1318013B1

    公开(公告)日：2003-07-21

    申请号：ITMI20001315

    申请日：2000-06-13

    Applicant: ST MICROELECTRONICS SRL

    Inventor： LISI CARLO ,  BEDARIDA LORENZO ,  GERACI ANTONINO ,  DIMA VINCENZO

    IPC: G11C16/28

    Abstract: The present invention relates a circuit arrangement for the lowering of the threshold voltage of a diode configured transistor comprising a mirror transistor, a first transistor and a second transistor, said mirror transistor and said first transistor having in common the gate electrodes in a circuit node, said second transistor being connected in a transdiode configuration and placed between the gate electrode and the drain electrode of said first transistor, and a current source being connected to the gate electrode of said first transistor and to the drain electrode of said second transistor, characterized by comprising a third transistor which is configured to receive a switching signal at its gate electrode and is connected between the drain and the gate electrode of said first transistor.

    5.
    发明专利
    未知

    公开(公告)号：ITMI20001315A1

    公开(公告)日：2001-12-13

    申请号：ITMI20001315

    申请日：2000-06-13

    Applicant: ST MICROELECTRONICS SRL

    Inventor： BEDARIDA LORENZO ,  GERACI ANTONINO ,  LISI CARLO ,  DIMA VINCENZO

    IPC: G11C16/28

    Abstract: The present invention relates a circuit arrangement for the lowering of the threshold voltage of a diode configured transistor comprising a mirror transistor, a first transistor and a second transistor, said mirror transistor and said first transistor having in common the gate electrodes in a circuit node, said second transistor being connected in a transdiode configuration and placed between the gate electrode and the drain electrode of said first transistor, and a current source being connected to the gate electrode of said first transistor and to the drain electrode of said second transistor, characterized by comprising a third transistor which is configured to receive a switching signal at its gate electrode and is connected between the drain and the gate electrode of said first transistor.

    6.
    发明专利
    未知

    公开(公告)号：DE60041056D1

    公开(公告)日：2009-01-22

    申请号：DE60041056

    申请日：2000-08-16

    Applicant: ST MICROELECTRONICS SRL

    Inventor： GERACI ANTONINO ,  LISI CARLO ,  BEDARIDA LORENZO ,  SFORZIN MARCO

    IPC: G11C16/28 ,  G11C7/12

    Abstract: A direct-comparison reading circuit for a nonvolatile memory array (2) having a plurality of memory cells (4) arranged in rows and columns (9), and at least one bit line (7), includes at least one array line (13), selectively connectable to the bit line (7), and a reference line (14); a precharging circuit (17) for precharging the array line (13) and reference line (14) at a preset precharging potential (VPC); at least one comparator (35) having a first terminal connected to the array line (13), and a second terminal connected to the reference line (14); and an equalization circuit (15, 23, 26) for equalizing the potentials of the array line (13) and reference line (14) in the precharging step. In addition, the reading circuit includes an equalization line (15) distinct from the reference line (14); and controlled switches (23, 26) for connecting, in the precharging step, the equalization line (15) to the array line (13) and to the reference line (14), and for disconnecting the equalization line (15) from the array line (13) and from the reference line (14) at the end of the precharging step.

    8.
    发明专利
    未知

    公开(公告)号：ITMI20001315D0

    公开(公告)日：2000-06-13

    申请号：ITMI20001315

    申请日：2000-06-13

    Applicant: ST MICROELECTRONICS SRL

    Inventor： BEDARIDA LORENZO ,  GERACI ANTONINO ,  LISI CARLO ,  DIMA VINCENZO

    IPC: G11C16/28

    Abstract: The present invention relates a circuit arrangement for the lowering of the threshold voltage of a diode configured transistor comprising a mirror transistor, a first transistor and a second transistor, said mirror transistor and said first transistor having in common the gate electrodes in a circuit node, said second transistor being connected in a transdiode configuration and placed between the gate electrode and the drain electrode of said first transistor, and a current source being connected to the gate electrode of said first transistor and to the drain electrode of said second transistor, characterized by comprising a third transistor which is configured to receive a switching signal at its gate electrode and is connected between the drain and the gate electrode of said first transistor.

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