2.
    发明专利
    未知

    公开(公告)号:DE102007051192A1

    公开(公告)日:2008-06-05

    申请号:DE102007051192

    申请日:2007-10-25

    Abstract: A memory device may include an array of addressable three-level cells, a coding circuit being input with three-bit strings and generating corresponding ternary strings based upon a code, and a program circuit being input with the ternary strings and storing them in respective pairs of three-level cells. The memory device also may include a read circuit reading stored ternary strings in the respective pairs of three-level cells, and a decoding circuit being input with the stored ternary strings and generating corresponding strings of three bits based upon the code.

    3.
    发明专利
    未知

    公开(公告)号:DE69923289D1

    公开(公告)日:2005-02-24

    申请号:DE69923289

    申请日:1999-04-28

    Abstract: Semiconductor device comprising at least two pads (101, 102; 103, 104) for the input of external signals and/or for the output of signals from said semiconductor device, at least two uncoupling buffers (201, 202; 203, 204) each connected to each one of said pads, at least one multiplexer (10; 20) connected to said pads (101, 102; 103, 104) by means of said uncoupling buffers (201, 202; 203, 204) and at least one memory element (4; 5) suitable to generate a configuration signal (C ) operating on said multiplexer (10; 20) and said uncoupling buffers (201, 202; 203, 204) to selectively enable one or the other of said pads (101, 102; 103, 104).

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