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    MINUTE CONTACT AREA IN SEMICONDUCTOR DEVICE, HIGH PERFORMANCE PHASE CHANGE MEMORY CELL AND METHOD OF MANUFACTURING THE MEMORY CELL
    1.
    发明专利
    MINUTE CONTACT AREA IN SEMICONDUCTOR DEVICE, HIGH PERFORMANCE PHASE CHANGE MEMORY CELL AND METHOD OF MANUFACTURING THE MEMORY CELL 有权

    公开(公告)号：JP2003174144A

    公开(公告)日：2003-06-20

    申请号：JP2002353352

    申请日：2002-12-05

    Applicant: ST MICROELECTRONICS SRL ,  OVONYX INC

    Inventor： BEZ ROBERTO ,  PELLIZZER FABIO ,  RIVA CATERINA ,  ZONCA ROMINA

    IPC: H01L27/10 ,  G11C16/02 ,  H01L27/105 ,  H01L27/24 ,  H01L45/00

    Abstract: PROBLEM TO BE SOLVED: To provide a high performance phase change memory cell of the minute contact structure. SOLUTION: The contact structure comprises a first conductive area having a first thin film portion of a first sublithographic size in a first direction, and a second conductive area having a second thin film portion of a second sublithographic size in a second direction crossing the first direction. The first and second thin film portions are electrically in contact with each other to form a contact surface including the sublithographic extending area. The thin film portions are formed with a deposition method in place of the lithography method. The first thin film portion is deposited to the wall of an aperture within a first dielectric material layer. The second thin film portion may be formed by depositing a sacrifice area to the perpendicular wall of a first limit layer, depositing a second limit layer to the side surface where the sacrifice area is not deposited, removing thereafter the sacrifice area, forming a sublithographic aperture for etching the mold aperture in the mold layer, and then filling the mold aperture. COPYRIGHT: (C)2003,JPO

    SUBSTRATE-LEVEL ASSEMBLY FOR AN INTEGRATED DEVICE, MANUFACTURING PROCESS THEREOF AND RELATED INTEGRATED DEVICE
    2.
    发明申请
    SUBSTRATE-LEVEL ASSEMBLY FOR AN INTEGRATED DEVICE, MANUFACTURING PROCESS THEREOF AND RELATED INTEGRATED DEVICE 审中-公开
    用于集成设备的基板级组件，其制造工艺以及相关的集成设备

    公开(公告)号：WO2007042336A2

    公开(公告)日：2007-04-19

    申请号：PCT/EP2006064298

    申请日：2006-07-14

    Applicant: ST MICROELECTRONICS SRL ,  COMBI CHANTAL ,  VIGNA BENEDETTO ,  ZIGLIOLI FEDERICO GIOVANNI ,  BALDO LORENZO ,  MAGUGLIANI MANUELA ,  LASALANDRA ERNESTO ,  RIVA CATERINA

    Inventor： COMBI CHANTAL ,  VIGNA BENEDETTO ,  ZIGLIOLI FEDERICO GIOVANNI ,  BALDO LORENZO ,  MAGUGLIANI MANUELA ,  LASALANDRA ERNESTO ,  RIVA CATERINA

    IPC: B81B7/02

    CPC classification number: B81B7/0061 ,  B81B7/02 ,  B81B2201/0235 ,  B81B2201/0264 ,  B81C1/0023 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/1461 ,  H01L2924/3025 ,  H04R1/04 ,  H04R19/005 ,  H01L2924/00014 ,  H01L2924/00

    Abstract: In a substrate-level assembly (22), a device substrate (20) of semiconductor material has a top face (20a) and houses a first integrated device (1; 16), in particular provided with a buried cavity (3), formed within the device substrate (20), and with a membrane (4), suspended over the buried cavity (3) in the proximity of the top face (20a). A capping substrate (21) is coupled to the device substrate (20) above the top face (20a) so as to cover the first integrated device (1; 16), in such a manner that a first empty space (25) is provided above the membrane (4). Electrical-contact elements (28a, 28b) electrically connect the integrated device (1; 16) with the outside of the substrate-level assembly (22). In one embodiment, the device substrate (20) integrates at least a further integrated device (1', 10) provided with a respective membrane (4'); and a further empty space (25'), fluidically isolated from the first empty space (25), is provided over the respective membrane (4') of the further integrated device (1', 10).

    Abstract translation: 在衬底级组件（22）中，半导体材料的器件衬底（20）具有顶面（20a）并容纳第一集成器件（1; 16），所述第一集成器件特别设置有埋入腔（3） 在器件衬底（20）内并且具有在顶面（20a）附近悬置在掩埋腔（3）上的膜（4）。 封盖衬底（21）在顶面（20a）上方与器件衬底（20）耦合，以便以这样的方式覆盖第一集成器件（1; 16）：提供第一空的空间（25） 在膜（4）上方。 电接触元件（28a，28b）将集成装置（1; 16）与衬底级组件（22）的外部电连接。 在一个实施例中，所述装置基底（20）集成了至少另一个集成装置（1'，10），所述集成装置设置有相应的膜（4'）; 并且在另一集成装置（1'，10）的相应的膜（4'）上设置与第一空的空间（25）流体隔离的另一个空的空间（25'）。

    PROCESS FOR MANUFACTURING AN INTERACTION STRUCTURE FOR A STORAGE MEDIUM
    3.
    发明申请
    PROCESS FOR MANUFACTURING AN INTERACTION STRUCTURE FOR A STORAGE MEDIUM 审中-公开
    用于制造存储介质的交互结构的过程

    公开(公告)号：WO2007113878A8

    公开(公告)日：2008-06-12

    申请号：PCT/IT2006000229

    申请日：2006-04-06

    Applicant: ST MICROELECTRONICS SRL ,  RIVA CATERINA ,  MURARI BRUNO ,  FRATTINI GIOVANNI

    Inventor： RIVA CATERINA ,  MURARI BRUNO ,  FRATTINI GIOVANNI

    IPC: G11B9/00

    CPC classification number: G11B9/1409 ,  B82Y10/00 ,  G11B9/14

    Abstract: Described herein is a process for manufacturing an interaction structure for a storage medium, which envisages forming a first interaction head provided with a first conductive region having a sub-lithographic smaller dimension (W 1 ). The step of forming a first interaction head (7) envisages: forming on a surface (14) a first delimitation region (15) having a side wall; depositing a conductive portion (16b) having a deposition thickness substantially matching the sub- lithographic smaller dimension (W 1 ) on the side wall; and then defining the conductive portion. The sub- lithographic smaller dimension (W 1 ) is between 1 and 50 nm, preferably 20 nm.

    Abstract translation: 本文描述了一种制造用于存储介质的相互作用结构的方法，其设想形成具有次平版印刷尺寸较小的第一导电区域的第一相互作用头（W1＆lt; 1＆gt;）。 形成第一相互作用头（7）的步骤设想：在表面（14）上形成具有侧壁的第一定界区域（15）; 沉积具有基本上与侧面壁上的亚光刻较小尺寸（W 1> 1）相匹配的沉积厚度的导电部分（16b）; 然后限定导电部分。 亚光刻尺寸较小（W 1 N 1）在1至50nm之间，优选20nm。

    7.
    发明专利
    未知

    公开(公告)号：AT552510T

    公开(公告)日：2012-04-15

    申请号：AT09177168

    申请日：2009-11-26

    Applicant: ST MICROELECTRONICS SRL

    Inventor： RIVA CATERINA ,  MORELLI MARCO ,  MARCHESI MARCO

    IPC: G01R33/05 ,  G01R33/07

    Abstract: A magnetic sensor is formed by a fluxgate sensor and by at least one Hall sensor integrated in a same integrated device, wherein the magnetic core of the fluxgate sensor is formed by a magnetic region that operates also as a concentrator for the Hall sensor. The magnetic region is manufactured in a post-machining stage on the metallization layers wherein the energizing coil and sensing coil of the fluxgate sensor are formed; the energizing and sensing coils are formed on a semiconductor substrate housing the conductive regions of the Hall sensor.

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