公开(公告)号：WO2007006764A2

公开(公告)日：2007-01-18

申请号：PCT/EP2006/064035

申请日：2006-07-07

Applicant: STMICROELECTRONICS S.r.l. ,  ARENA, Giuseppe ,  DONATO, Caterina ,  CAMALLERI, Cateno Marco ,  MAGRI', Angelo

Inventor： ARENA, Giuseppe ,  DONATO, Caterina ,  CAMALLERI, Cateno Marco ,  MAGRI', Angelo

IPC: H01L21/336 ,  H01L29/78 ,  H01L29/423 ,  H01L29/51

CPC classification number: H01L29/7813 ,  H01L29/0623 ,  H01L29/0878 ,  H01L29/42368 ,  H01L29/4933 ,  H01L29/511 ,  H01L29/66734

Abstract: A trench (5) is formed in a semiconductor body (2); the side walls and the bottom of the trench are covered with a first dielectric material layer (9); the trench (5) is filled with a second dielectric material layer (10); the first and the second dielectric material layers (9, 10) are etched via a partial, simultaneous and controlled etching such that the dielectric materials have similar etching rates; a gate-oxide layer (13) having a thickness smaller than the first dielectric material layer (9) is deposited on the walls of the trench (5); a gate region (14) of conductive material is formed within the trench (5); and body regions (7) and source regions (8) are formed within the semiconductor body (2), at the sides of and insulated from the gate region (14). Thereby, the gate region (14) extends only on top of the remaining portions of the first and second dielectric material layers (9, 10).

Abstract translation: 沟槽（5）形成在半导体本体（2）中; 沟槽的侧壁和底部被第一介电材料层（9）覆盖; 沟槽（5）填充有第二电介质层（10）; 通过部分，同时和受控的蚀刻蚀刻第一和第二介电材料层（9,10），使得介电材料具有相似的蚀刻速率; 在沟槽（5）的壁上沉积具有小于第一介电材料层（9）的厚度的栅极 - 氧化物层（13）。 在沟槽（5）内形成导电材料的栅区（14）; 并且在半导体本体（2）中，在栅极区域（14）的侧面和与栅极区域（14）绝缘的位置上形成有主体区域（7）和源极区域（8）。 因此，栅极区域（14）仅在第一和第二介电材料层（9,10）的剩余部分的顶部延伸。

公开(公告)号：WO2007116420A1

公开(公告)日：2007-10-18

申请号：PCT/IT2006/000244

申请日：2006-04-11

Applicant: STMICROELECTRONICS S.R.L. ,  LORENTI, Simona ,  CAMALLERI, Cateno Marco ,  SAGGIO, Mario, Giuseppe ,  FRISINA, Ferruccio

Inventor： LORENTI, Simona ,  CAMALLERI, Cateno Marco ,  SAGGIO, Mario, Giuseppe ,  FRISINA, Ferruccio

IPC: H01L29/06 ,  H01L29/78 ,  H01L21/336 ,  H01L21/20 ,  H01L21/205 ,  H01L21/324 ,  H01L21/3065 ,  H01L21/306 ,  H01L29/10 ,  H01L29/739 ,  H01L29/732

CPC classification number: H01L21/3247 ,  H01L21/02057 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/3065 ,  H01L21/324 ,  H01L27/088 ,  H01L29/045 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/66333 ,  H01L29/66712 ,  H01L29/73 ,  H01L29/7395 ,  H01L29/7802 ,  H01L29/8611 ,  H01L29/872

Abstract: Process for manufacturing a semiconductor power device, wherein a trench (8) is formed in a semiconductor body (2) having a first conductivity type; the trench is annealed for shaping purpose (8a) ; and the trench (8a) is filled with semiconductor material via epitaxial growth so as to obtain a first column (9) having a second conductivity type. The epitaxial growth is performed by supplying a gas containing silicon and a gas containing dopant ions of the second conductivity type in presence of a halogenide gas and occurs with uniform distribution of the dopant ions. The flow of the gas containing dopant ions is varied according to a linear ramp during the epitaxial growth; in particular, in the case of selective growth of the semiconductor material in the presence of a hard mask, the flow decreases; in the case of non-selective growth, in the absence of hard mask, the flow increases .

Abstract translation: 一种制造半导体功率器件的方法，其中在具有第一导电类型的半导体本体（2）中形成沟槽（8） 沟槽退火成型目的（8a）; 并且沟槽（8a）通过外延生长填充半导体材料，从而获得具有第二导电类型的第一列（9）。 外延生长通过在卤化物气体的存在下供给包含硅和含有第二导电类型的掺杂剂离子的气体进行，并且以掺杂剂离子的均匀分布发生。 含气体掺杂剂离子的流动在外延生长期间根据线性斜坡而变化; 特别是在硬掩模存在下选择性地生长半导体材料的情况下，流量减少; 在非选择性生长的情况下，在没有硬掩模的情况下，流动增加。

公开(公告)号：EP4047664A1

公开(公告)日：2022-08-24

申请号：EP22155166.6

申请日：2022-02-04

Applicant: STMicroelectronics S.r.l.

Inventor： SAGGIO, Mario Giuseppe ,  GUARNERA, Alfio ,  CAMALLERI, Cateno Marco

IPC: H01L29/49 ,  H01L29/78 ,  H01L21/336

Abstract: A vertical-conduction MOSFET device (50) formed in a body (55) of silicon carbide having a first and a second face (52A, 52B) and a peripheral zone (87). A drain region (57), of a first conductivity type, extends in the body (55) between the two faces. A body region (60), of a second conductivity type, extends in the body from the first face (55A), and a source region (65), having the first conductivity type, extends to the inside of the body region (60) from the first face (55A) of the body. An insulated gate region (70) extends on the first face of the body and comprises a gate conductive region (72). An annular connection region (86), of conductive material, is formed within a surface edge structure extending on the first face (55A) of the body (55), in the peripheral zone (87). The gate conductive region (72) and the annular connection region (86) are formed by a silicon layer and by a metal silicide layer overlying the silicon layer.

公开(公告)号：EP4307384A3

公开(公告)日：2024-02-07

申请号：EP23181494.8

申请日：2023-06-26

Applicant: STMicroelectronics S.r.l.

Inventor： CAMALLERI, Cateno Marco ,  SAGGIO, Mario Giuseppe ,  GUARNERA, Alfio

IPC: H01L29/06 ,  H01L29/49 ,  H01L29/78 ,  H01L29/423

Abstract: A power MOSFET device (1) comprises a semiconductor body (3) having a first main surface (3a). The semiconductor body (3) includes an active area (7) facing the first main surface (3a). The power MOSFET device (1) comprises an isolated-gate structure (15), which extends over the active area (7) and includes a gate-oxide layer (12), which is made of insulating material and extends over the first main surface (3a), and a gate region (24) buried in the gate-oxide layer (12) so as to be electrically insulated from the semiconductor body (3). The gate region (24) comprises a gate layer (14) of polysilicon and at least one first silicide region (25a) and one second silicide region (25b), which extend in the gate layer (14) so as to face a top surface (14a) of the gate layer (14) and to be arranged alongside one another and spaced apart from one another in a first plane (XY).

公开(公告)号：EP4333027A1

公开(公告)日：2024-03-06

申请号：EP23190768.4

申请日：2023-08-10

Applicant: STMicroelectronics S.r.l.

Inventor： SAGGIO, Mario Giuseppe ,  CAMALLERI, Cateno Marco ,  BELLOCCHI, Gabriele ,  RASCUNA', Simone

IPC: H01L21/336 ,  H01L29/45 ,  H01L29/78 ,  H01L29/12

Abstract: Method of manufacturing an electronic device (20), comprising forming an ohmic contact (59; 61) at an implanted region (26; 55) of a semiconductor body (48). Forming the ohmic contact provides for performing a high-temperature thermal process for allowing a reaction between a metal material and the material of the semiconductor body, for forming a silicide of the metal material. The step of forming the ohmic contact is performed prior to a step of forming one or more electrical structures (52, 56) which include materials that may be damaged by the high temperature of the thermal process of forming the silicide.

公开(公告)号：EP4328967A1

公开(公告)日：2024-02-28

申请号：EP23190203.2

申请日：2023-08-08

Applicant: STMicroelectronics S.r.l.

Inventor： SCALIA, Laura Letizia ,  CAMALLERI, Cateno Marco ,  ZANETTI, Edoardo ,  RUSSO, Alfio

IPC: H01L23/525 ,  H01L29/78 ,  H01L23/62

Abstract: SiC-based MOSFET electronic device (20; 30) comprising: a solid body (48); a gate terminal (24), extending into the solid body (48); a conductive path (36), extending at a first side of the solid body (48), configured to be electrically coupeable to a generator (23) of a biasing voltage (V GS ); a protection element (21) of a solid-state material, coupled to the gate terminal (24) and to the conductive path (36), the protection element (21) forming an electronic connection between the gate terminal (24) and the conductive path (36), and being configured to go from the solid state to a melted or gaseous state, interrupting the electrical connection, in response to a leakage current (i SC ) through the protection element (21) greater than a critical threshold; a buried cavity (69) in the solid body (48) accommodating, at least in part, the protection element (21).

公开(公告)号：EP4307384A2

公开(公告)日：2024-01-17

申请号：EP23181494.8

申请日：2023-06-26

Applicant: STMicroelectronics S.r.l.

Inventor： CAMALLERI, Cateno Marco ,  SAGGIO, Mario Giuseppe ,  GUARNERA, Alfio

IPC: H01L29/06 ,  H01L29/49 ,  H01L29/78 ,  H01L29/423

Abstract: A power MOSFET device (1) comprises a semiconductor body (3) having a first main surface (3a). The semiconductor body (3) includes an active area (7) facing the first main surface (3a). The power MOSFET device (1) comprises an isolated-gate structure (15), which extends over the active area (7) and includes a gate-oxide layer (12), which is made of insulating material and extends over the first main surface (3a), and a gate region (24) buried in the gate-oxide layer (12) so as to be electrically insulated from the semiconductor body (3). The gate region (24) comprises a gate layer (14) of polysilicon and at least one first silicide region (25a) and one second silicide region (25b), which extend in the gate layer (14) so as to face a top surface (14a) of the gate layer (14) and to be arranged alongside one another and spaced apart from one another in a first plane (XY).

公开(公告)号：EP4036986A1

公开(公告)日：2022-08-03

申请号：EP22154043.8

申请日：2022-01-28

Applicant: STMicroelectronics S.r.l.

Inventor： SAGGIO, Mario Giuseppe ,  ZANETTI, Edoardo ,  FRAZZETTO, Alessia Maria ,  GUARNERA, Alfio ,  CAMALLERI, Cateno Marco ,  GRIMALDI, Antonio Giuseppe

IPC: H01L29/10 ,  H01L29/66 ,  H01L29/16 ,  H01L29/78 ,  H01L21/04 ,  H01L29/417

Abstract: The vertical conduction MOSFET device (100)is formed by a body (105) of silicon carbide, which has a first type of conductivity and a face (105A), and by a superficial body region (115) of a second type of conductivity, which has a first doping level, extends into the body, from the face of the body, to a first depth (d sb ) along a first direction, and has a first width (W sb ) along a second direction transversal to the first direction. The MOSFET device is also formed by a source region (120) and by a deep body region (110). The source region is of the first type of conductivity, extends to the inside of the superficial body region, from the face of the body, to a second depth (d b ), along the first direction, and has a second width (W s ) along the second direction, wherein the second depth is smaller than the first depth and the second width is smaller than the first width. The deep body region is of the second type of conductivity, has a second doping level and extends into the body, at a distance from the face of the body and in direct electrical contact with the superficial body region, wherein the second doping level is higher than the first doping level.