公开(公告)号：US20240324103A1

公开(公告)日：2024-09-26

申请号：US18613202

申请日：2024-03-22

Applicant: IBIDEN CO., LTD.

Inventor： Masashi KUWABARA ,  Jun SAKAI ,  Shiho FUKUSHIMA

IPC: H05K1/11 ,  H05K1/03 ,  H05K3/16

CPC classification number: H05K1/115 ,  H05K1/0306 ,  H05K3/16 ,  H05K2201/0209 ,  H05K2201/0242 ,  H05K2201/0266 ,  H05K2201/032 ,  H05K2201/09536

Abstract: A wiring substrate includes a core substrate including a through-hole conductor, a first resin insulating layer, a first conductor layer including a seed layer and an electrolytic plating layer, a via conductor formed such that the via conductor electrically connects the through-hole conductor and first conductor layer, and a second resin insulating layer covering the first conductor layer. The core substrate includes a glass substrate such that the through-hole conductor is penetrating through the glass substrate, the seed layer includes a first layer formed on the first resin insulating layer and a second layer formed on the first layer, and the first conductor layer includes a conductor circuit such that a width of the first layer is larger than a width of the second layer in the conductor circuit and a width of the electrolytic plating layer is larger than the width of the first layer in the conductor circuit.

公开(公告)号：US20240306299A1

公开(公告)日：2024-09-12

申请号：US18595674

申请日：2024-03-05

Applicant: IBIDEN CO., LTD.

Inventor： Toshiki FURUTANI ,  Kyohei YOSHIKAWA ,  Takuya INISHI ,  Jun SAKAI

IPC: H05K1/11 ,  H05K1/03 ,  H05K3/16 ,  H05K3/18

CPC classification number: H05K1/116 ,  H05K1/0306 ,  H05K3/181 ,  H05K3/16 ,  H05K2201/032 ,  H05K2201/09536

Abstract: A wiring substrate includes a core substrate including a through-hole conductor, a resin insulating layer formed on the core substrate, a conductor layer formed on a surface of the resin insulating layer and including a seed layer and an electrolytic plating layer formed on the seed layer, and a via conductor formed in the resin insulating layer such that the via conductor is connected to the through-hole conductor in the core substrate and includes the seed layer and electrolytic plating layer extending from the conductor layer. The core substrate includes a glass substrate such that the through-hole conductor is formed in a through hole penetrating through the glass substrate, and the conductor layer and via conductor are formed such that the seed layer is formed by sputtering and includes an alloy including copper, aluminum, and one or more metals selected from nickel, zinc, gallium, silicon, and magnesium.

公开(公告)号：US20240306297A1

公开(公告)日：2024-09-12

申请号：US18601668

申请日：2024-03-11

Applicant: Apple Inc.

Inventor： Anne M. Mason ,  Chad O. Simpson ,  William Hannon ,  Mark J. Beesley

IPC: H05K1/11 ,  H05K3/00 ,  H05K3/42

CPC classification number: H05K1/115 ,  H05K3/0047 ,  H05K3/422 ,  H05K3/423 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2203/107

Abstract: Structures that implement three-dimensional (3D) conductive material (e.g., copper) in printed circuit boards (PCBs) are disclosed. 3D (three-dimensional) conductive material may include trenches and/or buried vias that are filled with conductive material in the PCBs. Trenches may be formed in build-up layers of a PCB by overlapping multiple laser drilled vias. The trenches may be filled with conductive material using electroplating process(es). Buried vias may be formed through the core layers of the PCB by mechanical drilling. The buried via may be filled with solid conductive material using a combination of electroless plating and electrolytic plating of conductive material. Various PCB structures are disclosed that implement combinations of these trenches and/or these buried vias filled with conductive material.

公开(公告)号：US11956898B2

公开(公告)日：2024-04-09

申请号：US17119126

申请日：2020-12-11

Applicant: Apple Inc.

Inventor： Anne M. Mason ,  Chad O. Simpson ,  William Hannon ,  Mark J. Beesley

IPC: H05K1/11 ,  H05K3/00 ,  H05K3/42

CPC classification number: H05K1/115 ,  H05K3/0047 ,  H05K3/422 ,  H05K3/423 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2203/107

Abstract: Structures that implement three-dimensional (3D) conductive material (e.g., copper) in printed circuit boards (PCBs) are disclosed. 3D (three-dimensional) conductive material may include trenches and/or buried vias that are filled with conductive material in the PCBs. Trenches may be formed in build-up layers of a PCB by overlapping multiple laser drilled vias. The trenches may be filled with conductive material using electroplating process(es). Buried vias may be formed through the core layers of the PCB by mechanical drilling. The buried via may be filled with solid conductive material using a combination of electroless plating and electrolytic plating of conductive material. Various PCB structures are disclosed that implement combinations of these trenches and/or these buried vias filled with conductive material.

公开(公告)号：US20230262890A1

公开(公告)日：2023-08-17

申请号：US17938977

申请日：2022-09-07

Applicant: Unimicron Technology Corp.

Inventor： Chih-Chiang Lu ,  Chi-Min Chang ,  Ming-Hao Wu ,  Yi-Pin Lin ,  Tung-Chang Lin ,  Jun-Rui Huang

IPC: H05K1/11 ,  H05K1/02

CPC classification number: H05K1/115 ,  H05K1/0222 ,  H05K2201/0195 ,  H05K2201/09536 ,  H05K2201/09809

Abstract: A circuit board structure includes a substrate, a first build-up structure layer, first and second external circuit layers, at least one first conductive via, and second conductive vias. The first build-up structure layer is disposed on a first circuit layer of the substrate. The first external circuit layer is disposed on the first build-up structure layer. The second external circuit layer is disposed on a second circuit layer and a portion of a third dielectric layer of the substrate. The first conductive via is electrically connected to the first external circuit layer and the second external circuit layer to define a signal path. The second conductive vias surround the first conductive via, and the first external circuit layer, the second conductive vias, the first circuit layer, the outer conductive layer, and the second external circuit layer define a first ground path. The first ground path surrounds the signal path.

公开(公告)号：US20190075662A1

公开(公告)日：2019-03-07

申请号：US16181180

申请日：2018-11-05

Applicant: SANMINA CORPORATION

Inventor： Shinichi Iketani ,  Dale Kersten

IPC: H05K3/42 ,  H05K1/11 ,  H05K1/02

CPC classification number: H05K3/429 ,  H05K1/0251 ,  H05K1/115 ,  H05K2201/0187 ,  H05K2201/09536 ,  H05K2201/09645 ,  H05K2203/061 ,  H05K2203/0713 ,  Y10T29/49165

Abstract: A multilayer printed circuit board is provided having a first dielectric layer and a first plating resist selectively positioned in the first dielectric layer. A second plating resist may be selectively positioned in the first dielectric layer or a second dielectric layer, the second plating resist separate from the first plating resist. A through hole extends through the first dielectric layer, the first plating resist, and the second plating resist. An interior surface of the through hole is plated with a conductive material except along a length between the first plating resist and the second plating resist. This forms a partitioned plated through hole having a first via segment electrically isolated from a second via segment.

公开(公告)号：US20180092222A1

公开(公告)日：2018-03-29

申请号：US15723135

申请日：2017-10-02

Applicant: SANMINA CORPORATION

Inventor： Shinichi Iketani ,  Dale Kersten

IPC: H05K3/42 ,  H05K1/11

CPC classification number: H05K3/429 ,  H05K1/0251 ,  H05K1/115 ,  H05K2201/0187 ,  H05K2201/09536 ,  H05K2201/09645 ,  H05K2203/061 ,  H05K2203/0713 ,  Y10T29/49165

Abstract: A multilayer printed circuit board is provided having a first dielectric layer and a first plating resist selectively positioned in the first dielectric layer. A second plating resist may be selectively positioned in the first dielectric layer or a second dielectric layer, the second plating resist separate from the first plating resist. A through hole extends through the first dielectric layer, the first plating resist, and the second plating resist. An interior surface of the through hole is plated with a conductive material except along a length between the first plating resist and the second plating resist. This forms a partitioned plated through hole having a first via segment electrically isolated from a second via segment.

公开(公告)号：US20180026666A1

公开(公告)日：2018-01-25

申请号：US15216615

申请日：2016-07-21

Applicant: QUALCOMM Incorporated

Inventor： Changhan Yun ,  Chengjie Zuo ,  Mario Velez ,  Niranjan Sunil Mudakatte ,  Shiqun Gu ,  Jonghae Kim ,  David Berdy

IPC: H04B1/16 ,  H01L21/48 ,  H01L23/498 ,  H01L23/66 ,  H01L27/01 ,  H01L49/02

CPC classification number: H04B1/1638 ,  H01F17/0013 ,  H01L21/4853 ,  H01L21/486 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5223 ,  H01L23/64 ,  H01L23/66 ,  H01L24/19 ,  H01L24/20 ,  H01L27/01 ,  H01L28/10 ,  H01L28/40 ,  H01L2223/6616 ,  H01L2223/6672 ,  H01L2223/6677 ,  H01L2223/6688 ,  H01L2224/04105 ,  H01L2224/24195 ,  H01L2924/10253 ,  H01L2924/13091 ,  H01L2924/1421 ,  H01L2924/15153 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19105 ,  H04B1/006 ,  H05K1/165 ,  H05K1/185 ,  H05K3/4605 ,  H05K2201/09536 ,  H05K2201/097

Abstract: In an illustrative example, an apparatus includes a passive-on-glass (POG) device integrated within a glass substrate. The apparatus further includes a semiconductor die integrated within the glass substrate.

公开(公告)号：US20170290165A1

公开(公告)日：2017-10-05

申请号：US15467685

申请日：2017-03-23

Applicant: TDK CORPORATION

Inventor： Hitoshi SAITA

IPC: H05K1/18 ,  H01L23/00 ,  H05K3/32 ,  H01L21/48 ,  H05K3/00 ,  H05K3/46 ,  H05K3/30 ,  H01L23/498 ,  H05K1/11

CPC classification number: H01L21/486 ,  H01G4/33 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2224/16235 ,  H05K1/162 ,  H05K3/429 ,  H05K3/4644 ,  H05K2201/09536 ,  H05K2201/09672 ,  H05K2201/10015

Abstract: A thin film component sheet includes: a conducting interconnection layer formed of a conductor; an insulating layer that is laminated on the conducting interconnection layer and is formed of an insulating material; and a plurality of thin film electronic components, each of which has a pair of first and second electrode layers and a dielectric layer provided between the first and second electrode layers, and which are arranged to be separated on the insulating layer. In a state in which a main surface of the first electrode layer in each of the plurality of thin film electronic components is exposed to an outside on a main surface of one side of the thin film component sheet, a flat surface of the main surface of the thin film component sheet is formed,

公开(公告)号：US09781844B2

公开(公告)日：2017-10-03

申请号：US14205331

申请日：2014-03-11

Applicant: SANMINA CORPORATION

Inventor： Shinichi Iketani ,  Dale Kersten

IPC: H05K3/42 ,  H05K1/11 ,  H05K1/02

CPC classification number: H05K3/429 ,  H05K1/0251 ,  H05K1/115 ,  H05K2201/0187 ,  H05K2201/09536 ,  H05K2201/09645 ,  H05K2203/061 ,  H05K2203/0713 ,  Y10T29/49165

Abstract: A multilayer printed circuit board is provided having a first dielectric layer and a first plating resist selectively positioned in the first dielectric layer. A second plating resist may be selectively positioned in the first dielectric layer or a second dielectric layer, the second plating resist separate from the first plating resist. A through hole extends through the first dielectric layer, the first plating resist, and the second plating resist. An interior surface of the through hole is plated with a conductive material except along a length between the first plating resist and the second plating resist. This forms a partitioned plated through hole having a first via segment electrically isolated from a second via segment.