公开(公告)号：US12022621B2

公开(公告)日：2024-06-25

申请号：US17869035

申请日：2022-07-20

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Mi Jeong Jeon ,  Tae Hee Yoo ,  Hyun Seok Yang ,  In Jae Chung

IPC: H05K1/02 ,  G03F7/00 ,  H05K1/11 ,  H05K3/10 ,  H05K3/18

CPC classification number: H05K3/108 ,  G03F7/70466 ,  H05K1/0296 ,  H05K1/111 ,  H05K3/184 ,  H05K2201/09845 ,  H05K2203/0588 ,  H05K2203/072 ,  H05K2203/0723

Abstract: A method of manufacturing a printed circuit board includes: forming first and second resist films, respectively having first and second openings exposing a first metal layer disposed on one surface of an insulating layer; forming a second metal layer on the first metal layer, exposed through the first and second openings, to fill at least a portion of each of the first and second openings; and removing the first and second resist films. The first and second openings have different widths in a cross-section.

公开(公告)号：US11805595B2

公开(公告)日：2023-10-31

申请号：US17872082

申请日：2022-07-25

Applicant: Amphenol Corporation

Inventor： Marc Robert Charbonneau ,  Jose Ricardo Paniagua

IPC: H05K1/02 ,  H05K1/03 ,  H05K1/09 ,  H05K1/11 ,  H05K1/18 ,  H05K3/04 ,  H05K3/30 ,  H05K3/32 ,  H05K3/40 ,  H05K3/42 ,  H05K3/46 ,  H01R12/51 ,  H01R12/70 ,  H01R12/73 ,  H01R12/71

CPC classification number: H05K1/0245 ,  H01R12/7082 ,  H01R12/716 ,  H05K1/0219 ,  H05K1/0251 ,  H05K1/115 ,  H05K3/429 ,  H05K1/0225 ,  H05K2201/096 ,  H05K2201/09727 ,  H05K2201/09845

Abstract: A printed circuit board includes a plurality of layers including attachment layers and routing layers; and columns of via patterns formed in the plurality of layers, wherein via patterns in adjacent columns are offset in a direction of the columns, each of the via patterns comprising: first and second signal vias forming a differential signal pair, the first and second signal vias extending through at least the attachment layers; and at least one conductive shadow via located between the first and second signal vias of the differential pair. In some embodiments, at least one conductive shadow via is electrically connected to a conductive surface film.

公开(公告)号：US20190090362A1

公开(公告)日：2019-03-21

申请号：US16197405

申请日：2018-11-21

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Kuniaki YOSUI

IPC: H05K3/46

CPC classification number: H05K3/4691 ,  H05K1/0278 ,  H05K1/028 ,  H05K1/0284 ,  H05K1/0313 ,  H05K1/036 ,  H05K1/0393 ,  H05K1/111 ,  H05K1/118 ,  H05K1/119 ,  H05K1/14 ,  H05K1/18 ,  H05K3/4602 ,  H05K3/4614 ,  H05K3/4635 ,  H05K3/4652 ,  H05K2201/0129 ,  H05K2201/0141 ,  H05K2201/09845

Abstract: A multilayer board includes a first base material substrate including insulating base material layers that are laminated, a second base material substrate laminated on the first base material substrate to straddle a stepped portion, and a third base material substrate laminated on the second base material. The first base material substrate includes first and second conductor patterns respectively provided on surfaces in contact with the second base material substrate. The third base material substrate includes third and fourth conductor patterns. The second base material substrate includes a first interlayer connection conductor connecting the first and third conductor patterns, and a second interlayer connection conductor connecting the second and fourth conductor patterns, and has a higher flowability than the first and third base material substrates during lamination.

公开(公告)号：US10080287B2

公开(公告)日：2018-09-18

申请号：US14886790

申请日：2015-10-19

Applicant: Dell Products L.P.

Inventor： Kevin W. Mundt ,  Jason D. Adrian

IPC: H05K1/00 ,  H05K1/11 ,  H05K3/00 ,  H05K3/42 ,  H01R12/58 ,  H05K3/30 ,  H05K3/46

CPC classification number: H05K1/115 ,  H01R12/585 ,  H05K3/0047 ,  H05K3/0094 ,  H05K3/306 ,  H05K3/421 ,  H05K3/4611 ,  H05K2201/09509 ,  H05K2201/09845 ,  H05K2201/10189 ,  H05K2201/10545 ,  H05K2203/1476 ,  Y10T29/49126

Abstract: An information handling system circuit board interfaces storage device surface connectors and storage device controllers disposed on opposing sides by coupling a first circuit board portion having a controller press in connector to a second circuit board portion having plural surface connectors. The first and second circuit board portions couple to each other with an adhesive activated by curing. Resistant ink is printed over openings of the first circuit board portion where adhesive is applied in order to prevent the adhesive from flowing into the openings at or before the curing of the adhesive.

公开(公告)号：US10039179B2

公开(公告)日：2018-07-31

申请号：US15350262

申请日：2016-11-14

Applicant: NGK SPARK PLUG CO., LTD.

Inventor： Kensuke Matsuhashi

IPC: H05K1/02 ,  H05K1/03 ,  H05K1/11 ,  H01L23/367 ,  H01L23/498 ,  H05K1/18

CPC classification number: H05K1/0204 ,  H01L23/13 ,  H01L23/15 ,  H01L23/36 ,  H01L23/3675 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H05K1/0271 ,  H05K1/0306 ,  H05K1/115 ,  H05K1/18 ,  H05K3/403 ,  H05K3/4629 ,  H05K2201/09845 ,  H05K2201/10416

Abstract: A wiring substrate includes: a substrate body made from ceramic, having a front surface and a rear surface, and having a through hole penetrating between the front surface and the rear surface; and a heatsink inserted into the through hole. A step portion protruding in a direction perpendicular to an axial direction of the through hole, is formed over an entire periphery on an inner wall surface of the through hole of the substrate body. A flange opposed to the step portion is provided so as to protrude, over an entire periphery on a side surface of the heatsink. A stress relaxing ring is arranged over an entire periphery between the step portion and a joining surface opposed to the step portion. A brazing material is provided between the ring, and the joining surface and the step portion.

公开(公告)号：US20180206335A1

公开(公告)日：2018-07-19

申请号：US15923070

申请日：2018-03-16

Applicant: GigaLane Co., Ltd.

Inventor： Sang Pil KIM ,  Da Yeon Lee ,  Hwang Sub Koo ,  Hyun Je Kim ,  Hee Seok Jung

IPC: H05K1/02 ,  H05K3/28 ,  H05K3/40 ,  H05K3/00 ,  H05K3/06 ,  H05K1/11 ,  H05K3/46

CPC classification number: H05K1/0281 ,  H05K1/0219 ,  H05K1/024 ,  H05K1/0242 ,  H05K1/115 ,  H05K3/0026 ,  H05K3/0038 ,  H05K3/0044 ,  H05K3/06 ,  H05K3/28 ,  H05K3/4038 ,  H05K3/4644 ,  H05K2201/093 ,  H05K2201/09845 ,  H05K2203/0228 ,  H05K2203/107

Abstract: Provided are a flexible circuit board having enhanced bending durability and a method for preparing same. A method for preparing a flexible circuit board having enhanced bending durability, according to the present invention, comprises the steps of: (a) forming a signal line and a first ground layer on a first dielectric body and forming a second ground layer on the bottom side of the first dielectric body; (b) preparing a second dielectric body; (c) preparing a first bonding sheet and a first protective sheet which is connected to one end of the first boding sheet or of which one or more parts are overlapped on one end of the first bonding sheet; (d) bonding the second dielectric body onto the first dielectric body by means of the first bonding sheet; (e) forming a via hole such that the first ground layer and second ground layer can be conducted; and (f) cutting in the width direction the second dielectric body placed on the first protective sheet.

公开(公告)号：US20180166372A1

公开(公告)日：2018-06-14

申请号：US15866686

申请日：2018-01-10

Applicant: Shinko Electric Industries Co., Ltd.

Inventor： Noriyoshi SHIMIZU ,  Yusuke GOZU ,  Jun FURUICHI ,  Akio ROKUGAWA ,  Takashi Ito

IPC: H01L23/498 ,  H05K1/11 ,  H01L23/00 ,  H05K3/46 ,  H01L25/10 ,  H01L25/065 ,  H01L23/538 ,  H05K1/09 ,  H05K3/00 ,  H05K3/38

CPC classification number: H01L23/49822 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49894 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0655 ,  H01L25/105 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/26175 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32237 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/8149 ,  H01L2224/81801 ,  H01L2224/83104 ,  H01L2224/83855 ,  H01L2224/92125 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/3511 ,  H05K1/095 ,  H05K1/111 ,  H05K1/112 ,  H05K1/114 ,  H05K1/115 ,  H05K3/0073 ,  H05K3/383 ,  H05K3/4644 ,  H05K2201/0195 ,  H05K2201/09845 ,  H05K2203/0392 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/01079 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0665

Abstract: A wiring substrate includes a first wiring structure and a second wiring structure. The first wiring structure includes a first insulating layer, which covers a first wiring layer, and a via wiring. A first through hole of the first insulating layer is filled with the via wiring. The second wiring structure includes a second wiring layer and a second insulating layer. The second wiring layer is formed on an upper surface of the first insulating layer and an upper end surface of the via wiring. The second wiring layer partially includes a roughened surface. The second insulating layer is stacked on the upper surface of the first insulating layer and covers the second wiring layer. The second wiring structure has a higher wiring density than the first wiring structure. The roughened surface of the second wiring layer has a smaller surface roughness than the first wiring layer.

公开(公告)号：US20180097304A1

公开(公告)日：2018-04-05

申请号：US15827820

申请日：2017-11-30

Applicant: LG ELECTRONICS INC.

Inventor： Seunghak RYU

IPC: H01R12/77 ,  H01R13/62

CPC classification number: H01R12/774 ,  H01R12/81 ,  H01R13/6205 ,  H05K1/0298 ,  H05K1/118 ,  H05K3/361 ,  H05K2201/058 ,  H05K2201/09845

Abstract: A display device is disclosed. The display device includes a body, a housing separated from the body and configured to transmit/receive signals to/from the body, and a cable coupling the housing and the body, wherein the cable includes a flat cable located in at least part of the cable and having a flat shape, and a round cable located in at least another part of the cable and having a round shape. According to the present invention, the flat cable has a narrow width by including a plurality of layers, and thus wiring of signal terminals and power terminals can be easily changed between the flat cable and the round cable.

公开(公告)号：US20180070439A1

公开(公告)日：2018-03-08

申请号：US15807444

申请日：2017-11-08

Applicant: Amphenol Corporation

Inventor： Marc Robert Charbonneau ,  Jose Ricardo Paniagua

IPC: H05K1/02 ,  H05K1/11

CPC classification number: H05K1/0225 ,  H05K1/0219 ,  H05K1/0251 ,  H05K1/115 ,  H05K3/429 ,  H05K2201/0723 ,  H05K2201/096 ,  H05K2201/09727 ,  H05K2201/09845

Abstract: A printed circuit board includes a plurality of layers including conductive layers separated by dielectric layers, the conductive layers including a signal layer; and via patterns formed in the plurality of layers, each of the via patterns comprising first and second signal vias extending from a first surface of the printed circuit board to the signal layer, the signal layer including first and second signal traces connected to the first and second signal vias, respectively, the signal layer further including a ground conductor located between the signal traces and adjacent signal-carrying elements.

公开(公告)号：US20180062059A1

公开(公告)日：2018-03-01

申请号：US15673959

申请日：2017-08-10

Applicant: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.

Inventor： Masashi KICHIMA

IPC: H01L33/64 ,  H01L33/50 ,  H01L33/62 ,  H01L23/00 ,  F21V29/76 ,  F21S8/10 ,  F21V23/06

CPC classification number: H01L33/647 ,  F21S41/141 ,  F21S41/19 ,  F21S41/192 ,  F21S45/43 ,  F21S45/47 ,  F21V23/06 ,  F21V29/70 ,  F21V29/76 ,  F21V29/763 ,  F21Y2115/10 ,  H01L24/16 ,  H01L24/17 ,  H01L33/502 ,  H01L33/62 ,  H01L33/642 ,  H01L2224/13111 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1316 ,  H01L2224/14519 ,  H01L2224/73265 ,  H01L2924/12041 ,  H05K1/0204 ,  H05K2201/09827 ,  H05K2201/09845 ,  H05K2201/09854 ,  H05K2201/10106 ,  H05K2201/10416

Abstract: A light-emitting module is provided. The light-emitting module includes an insulating substrate. The insulating substrate includes a mounting surface, a rear surface, and a through hole that passes from the mounting surface to the rear surface. A light-emitting element is on the mounting surface. A thermal conductor is disposed in the through hole in contact with an inner wall of the insulating substrate defined by the through hole. The thermal conductor includes a mounting-side end face thermally connected to the light-emitting element, a rear-side end face, and a displacement suppressing portion that suppresses displacement of the thermal conductor in a direction from the rear surface to the mounting surface. thermal conductor. The rear-side end, in a cross-section parallel to the rear surface of the insulating surface, is larger in surface area than the mounting-side end, in a cross-section parallel to the mounting surface of the insulating substrate.