公开(公告)号：US09384806B2

公开(公告)日：2016-07-05

申请号：US14827292

申请日：2015-08-15

Applicant: Unity Semiconductor Corporation

Inventor： Christophe Chevallier ,  Seow Fong Lim ,  Chang Hua Siau

IPC: G11C11/34 ,  G11C7/22 ,  G11C5/02 ,  G11C11/21 ,  G11C13/00 ,  G11C8/10 ,  G11C8/12 ,  B82Y30/00 ,  G11C7/04

CPC classification number: G11C7/22 ,  B82Y30/00 ,  G11C5/02 ,  G11C7/04 ,  G11C8/10 ,  G11C8/12 ,  G11C11/21 ,  G11C13/0021

Abstract: A memory device includes a plurality of memory layers and a selecting circuit configured to select a delta value corresponding to a parameter of at least one of the plurality of memory layers having fabricated thereon at least one memory cell accessed during an operation. The memory device further includes an adjusting circuit configured to adjust an access signal based at least in part on the delta value, the access signal being configured to access the at least one memory cell during the operation.

Abstract translation: 存储器件包括多个存储器层和选择电路，该选择电路被配置为选择与在其上制造的至少一个存储器层的参数对应的增量值，所述存储器层中的至少一个存储器层具有在操作期间访问的至少一个存储器单元。 所述存储器件还包括调整电路，所述调整电路被配置为至少部分地基于所述增量值来调整接入信号，所述接入信号被配置为在所述操作期间访问所述至少一个存储器单元。

公开(公告)号：US09306549B2

公开(公告)日：2016-04-05

申请号：US14688060

申请日：2015-04-16

Applicant: Unity Semiconductor Corporation

Inventor： Christophe Chevallier ,  Chang Hua Siau

IPC: G11C11/34 ,  H03K3/356 ,  G11C13/00 ,  G11C8/08 ,  G11C8/10

CPC classification number: G11C13/0023 ,  G11C8/08 ,  G11C8/10 ,  G11C13/0007 ,  G11C13/0028 ,  G11C2213/31 ,  G11C2213/71 ,  G11C2213/77 ,  H03K3/356104 ,  H03K19/018521

Abstract: Circuitry for generating voltage levels operative to perform data operations on non-volatile re-writeable memory arrays are disclosed. In some embodiments an integrated circuit includes a substrate and a base layer formed on the substrate to include active devices configured to operate within a first voltage range. Further, the integrated circuit can include a cross-point memory array formed above the base layer and including re-writable two-terminal memory cells that are configured to operate, for example, within a second voltage range that is greater than the first voltage range. Conductive array lines in the cross-point memory array are electrically coupled with the active devices in the base layer. The integrated circuit also can include X-line decoders and Y-line decoders that include devices that operate in the first voltage range. The active devices can include other active circuitry such as sense amps for reading data from the memory cells, for example.

公开(公告)号：US20150364169A1

公开(公告)日：2015-12-17

申请号：US14827292

申请日：2015-08-15

Applicant: Unity Semiconductor Corporation

Inventor： Christophe Chevallier ,  Seow Fong Lim ,  Chang Hua Siau

IPC: G11C7/22 ,  G11C8/12 ,  G11C8/10

CPC classification number: G11C7/22 ,  B82Y30/00 ,  G11C5/02 ,  G11C7/04 ,  G11C8/10 ,  G11C8/12 ,  G11C11/21 ,  G11C13/0021

Abstract: Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement circuits configured to compensate for parameter variations in layers of memory by adjusting access signals during memory operations. In some embodiments, memory cells are based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes multiple layers of memory, a layer including sub-layers of semiconductor material. The integrated circuit also includes an access signal generator configured to generate an access signal to facilitate an access operation, and a characteristic adjuster configured to adjust the access signal for each layer in the multiple layers of memory.

公开(公告)号：US09159408B2

公开(公告)日：2015-10-13

申请号：US14167694

申请日：2014-01-29

Applicant: Unity Semiconductor Corporation

Inventor： Christophe J. Chevallier ,  Steve Kuo-Ren Hsia ,  Wayne Kinney ,  Steven Longcor ,  Darrell Rinerson ,  John Sanchez ,  Philip F. S. Swab ,  Edmond R. Ward

IPC: H01L45/00 ,  G11C13/00 ,  G11C11/16 ,  G11C11/56 ,  H01L27/24

CPC classification number: H01L27/2463 ,  G11C11/16 ,  G11C11/5685 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/004 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/009 ,  G11C2213/15 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/71 ,  G11C2213/77 ,  G11C2213/79 ,  H01L27/24 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1633 ,  H01L45/1658

Abstract: A memory cell including conductive oxide electrodes is disclosed. The memory cell includes a memory element operative to store data as a plurality of resistive states. The memory element includes a layer of a conductive metal oxide (CMO) (e.g., a perovskite) in contact with an electrode that may comprise one or more layers of material. At least one of those layers of material can be a conductive oxide (e.g., a perovskite such as LaSrCoO3-LSCoO or LaNiO3-LNO) that is in contact with the CMO. The conductive oxide layer can be selected as a seed layer operative to provide a good lattice match with and/or a lower crystallization temperature for the CMO. The conductive oxide layer may also be in contact with a metal layer (e.g., Pt). The memory cell additionally exhibits non-linear IV characteristics, which can be favorable in certain arrays, such as non-volatile two-terminal cross-point memory arrays.

Abstract translation: 公开了一种包括导电氧化物电极的存储单元。 存储单元包括用于将数据存储为多个电阻状态的存储元件。 存储元件包括与可包括一层或多层材料的电极接触的导电金属氧化物（CMO）（例如，钙钛矿）层。 这些材料层中的至少一层可以是与CMO接触的导电氧化物（例如，诸如LaSrCoO3-LSCoO或LaNiO3-LNO的钙钛矿）。 可以选择导电氧化物层作为晶种层，以为CMO提供良好的晶格匹配和/或较低的结晶温度。 导电氧化物层也可以与金属层（例如Pt）接触。 存储单元还具有非线性IV特性，这在某些阵列中是有利的，例如非易失性两端交叉点存储阵列。

公开(公告)号：US09117495B2

公开(公告)日：2015-08-25

申请号：US13935105

申请日：2013-07-03

Applicant: UNITY SEMICONDUCTOR CORPORATION

Inventor： Chang Hua Siau ,  Bruce Lynn Bateman

IPC: G11C5/06 ,  G11C5/08 ,  G11C7/00 ,  G11C7/18 ,  G11C13/00 ,  G11C7/04 ,  G11C7/12 ,  G11C16/24

CPC classification number: G11C5/06 ,  G11C5/08 ,  G11C7/00 ,  G11C7/04 ,  G11C7/12 ,  G11C7/18 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/004 ,  G11C13/0069 ,  G11C13/0097 ,  G11C16/24 ,  G11C2213/71

Abstract: A memory array includes wordlines, local bitlines, two-terminal memory elements, global bitlines, and local-to-global bitline pass gates and gain stages. The memory elements are formed between the wordlines and local bitlines. Each local bitline is selectively coupled to an associated global bitline, by way of an associated local-to-global bitline pass gate. During a read operation when a memory element of a local bitline is selected to be read, a local-to-global gain stage is configured to amplify a signal on or passing through the local bitline to an amplified signal on or along an associated global bitline. The amplified signal, which in one embodiment is dependent on the resistive state of the selected memory element, is used to rapidly determine the memory state stored by the selected memory element. The global bit line and/or the selected local bit line can be biased to compensate for the Process Voltage Temperature (PVT) variation.

Abstract translation: 存储器阵列包括字线，本地位线，双端存储器元件，全局位线以及局部到全局位线传递门​​和增益级。 存储元件形成在字线和本地位线之间。 每个本地位线通过相关联的局部到全局位线传递门​​选择性地耦合到相关联的全局位线。 在选择本地位线的存储元件被读取的读取操作期间，局部到全局增益级被配置为将本地位线上的信号放大到相关联的全局位线上或沿相关联的全局位线 。 在一个实施例中放大的信号取决于所选择的存储器元件的电阻状态，被用于快速地确定由所选择的存储器元件存储的存储器状态。 全局位线和/或选定的局部位线可被偏置以补偿过程电压温度（PVT）变化。

公开(公告)号：US09112499B2

公开(公告)日：2015-08-18

申请号：US13724789

申请日：2012-12-21

Applicant: Unity Semiconductor Corporation

Inventor： Robert Norman

IPC: H03K19/177

CPC classification number: H03K19/177 ,  H03K19/1776 ,  H03K19/17772 ,  H03K19/1778

Abstract: Field programmable gate arrays using resistivity-sensitive memories are described, including a programmable cell comprising a configurable logic, a memory connected to the configurable logic to provide functions for the configurable logic, the memory comprises a non-volatile rewriteable memory element including a resistivity-sensitive memory element, an input/output logic connected to the configurable logic and the memory to communicate with other cells. The memory elements may be two-terminal resistivity-sensitive memory elements that store data in the absence of power. The two-terminal memory elements may store data as plurality of conductivity profiles that can be non-destructively read by applying a read voltage across the terminals of the memory element and data can be written to the two-terminal memory elements by applying a write voltage across the terminals. The memory can be vertically configured in one or more memory planes that are vertically stacked upon each other and are positioned above a logic plane.

Abstract translation: 描述了使用电阻率敏感存储器的现场可编程门阵列，包括包括可配置逻辑的可编程单元，连接到可配置逻辑以提供可配置逻辑的功能的存储器，存储器包括非易失性可重写存储元件， 敏感存储器元件，连接到可配置逻辑的输入/输出逻辑和与其他单元通信的存储器。 存储器元件可以是在没有电力的情况下存储数据的两端电阻率敏感存储器元件。 两端存储器元件可以将数据存储为可以通过在存储器元件的端子上施加读取电压而被非破坏性地读取的多个导电率分布，并且可以通过施加写入电压将数据写入到两端存储器元件 跨越终端。 存储器可以垂直配置在一个或多个垂直堆叠在一起的并且位于逻辑平面之上的存储器平面中。

公开(公告)号：US20150132917A1

公开(公告)日：2015-05-14

申请号：US14526894

申请日：2014-10-29

Applicant: UNITY SEMICONDUCTOR CORPORATION

Inventor： Chang Hua Siau ,  Christophe Chevallier ,  Darrell Rinerson ,  Seow Fong Lim ,  Sri Rama Namala

IPC: H01L45/00 ,  G11C13/00 ,  H01L27/24

CPC classification number: G11C5/025 ,  G11C5/02 ,  G11C8/00 ,  G11C11/00 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2213/77 ,  H01L21/82 ,  H01L27/2481 ,  H01L45/16

Abstract: Embodiments relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement a memory architecture that includes local bit lines for accessing subsets of memory elements, such as memory elements based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes a cross-point memory array formed above a logic layer. The cross-point memory array includes X-lines and Y-lines, of which at least one Y-line includes groups of Y-line portions. Each of the Y-line portions can be arranged in parallel with other Y-line portions within a group of the Y-line portions. Also included are memory elements disposed between a subset of the X-lines and the group of the Y-line portions. In some embodiments, a decoder is configured to select a Y-line portion from the group of Y-line portions to access a subset of the memory elements.

Abstract translation: 实施例通常涉及半导体和存储器技术，更具体地，涉及用于实现存储器架构的系统，集成电路和方法，该存储器架构包括用于访问诸如基于第三维存储器技术的存储器元件的存储器元件的子集的本地位线。 在至少一些实施例中，集成电路包括形成在逻辑层上方的交叉点存储器阵列。 交叉点存储器阵列包括X线和Y线，其中至少一条Y线包括Y线部分的组。 每个Y线部分可以与一组Y线部分内的其它Y线部分平行地布置。 还包括设置在X线的子集和Y线部分的组之间的存储器元件。 在一些实施例中，解码器被配置为从Y组部分组中选择Y线部分以访问存储器元件的子集。

公开(公告)号：US20150055425A1

公开(公告)日：2015-02-26

申请号：US14476632

申请日：2014-09-03

Applicant: UNITY SEMICONDUCTOR CORPORATION

Inventor： Christophe Chevallier ,  Seow Fong Lim ,  Chang Hua Siau

IPC: G11C7/22

CPC classification number: G11C7/22 ,  B82Y30/00 ,  G11C5/02 ,  G11C7/04 ,  G11C8/10 ,  G11C8/12 ,  G11C11/21 ,  G11C13/0021

Abstract: Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement circuits configured to compensate for parameter variations in layers of memory by adjusting access signals during memory operations. In some embodiments, memory cells are based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes multiple layers of memory, a layer including sub-layers of semiconductor material. The integrated circuit also includes an access signal generator configured to generate an access signal to facilitate an access operation, and a characteristic adjuster configured to adjust the access signal for each layer in the multiple layers of memory.

Abstract translation: 本发明的实施例一般涉及半导体和存储器技术，更具体地，涉及用于实现电路的系统，集成电路和方法，所述电路被配置为通过在存储器操作期间调整存取信号来补偿存储器层中的参数变化。 在一些实施例中，存储器单元基于第三维存储器技术。 在至少一些实施例中，集成电路包括多层存储器，包括半导体材料子层的层。 集成电路还包括被配置为生成访问信号以便于访问操作的访问信号发生器，以及被配置为调整多层存储器中的每层的访问信号的特征调整器。

公开(公告)号：US20140231741A1

公开(公告)日：2014-08-21

申请号：US14062609

申请日：2013-10-24

Applicant: Unity Semiconductor Corporation

Inventor： Lidia Vereen ,  Bruce Lynn Bateman ,  Louis Parillo ,  Elizabeth Friend ,  David Eggleston

IPC: H01L45/00

CPC classification number: H01L45/145 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/12 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1666 ,  H01L45/1683

Abstract: In an example, a single damascene structure is formed by, for example, providing a dielectric layer, forming a void in the dielectric layer, and forming a portion of a first two-terminal resistive memory cell and a portion of a second two-terminal resistive memory cell within the void. The portions of the two-terminal resistive memory cells may be vertically stacked within the void.

Abstract translation: 在一个示例中，通过例如提供电介质层，在电介质层中形成空隙，以及形成第一两端电阻存储单元的一部分和第二两端的一部分，形成单个镶嵌结构 电阻记忆体在空隙内。 两端电阻式存储单元的部分可以垂直地堆叠在空隙内。

公开(公告)号：US20140140123A1

公开(公告)日：2014-05-22

申请号：US14068754

申请日：2013-10-31

Applicant: Unity Semiconductor Corporation

Inventor： Christophe Chevallier ,  Robert Norman

IPC: G11C5/00

CPC classification number: G11C13/0035 ,  G11C5/005 ,  G11C5/02 ,  G11C11/16 ,  G11C13/0002 ,  G11C13/0033 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2213/71 ,  G11C2213/77

Abstract: Circuitry and methods for restoring data in memory are disclosed. The memory may include at least one layer of a non-volatile two-terminal cross-point array that includes a plurality of two-terminal memory elements that store data as a plurality of conductivity profiles and retain stored data in the absence of power. Over a period of time, logic values indicative of the stored data may drift such that if the logic values are not restored, the stored data may become corrupted. At least a portion of each memory may have data rewritten or restored by circuitry electrically coupled with the memory. Other circuitry may be used to determine a schedule for performing restore operations to the memory and the restore operations may be triggered by an internal or an external signal or event. The circuitry may be positioned in a logic layer and the memory may be fabricated over the logic layer.

Abstract translation: 公开了用于恢复存储器中的数据的电路和方法。 存储器可以包括非易失性两端交叉点阵列的至少一层，其包括将数据存储为多个电导率分布并且在没有电力的情况下保存存储的数据的多个两端存储器元件。 在一段时间内，指示存储的数据的逻辑值可能漂移，使得如果逻辑值不被恢复，则所存储的数据可能被破坏。 每个存储器的至少一部分可以具有与存储器电耦合的电路重写或恢复的数据。 可以使用其他电路来确定用于对存储器执行恢复操作的调度，并且恢复操作可以由内部或外部信号或事件来触发。 电路可以定位在逻辑层中，并且存储器可以在逻辑层上制造。