公开(公告)号：US09049806B2

公开(公告)日：2015-06-02

申请号：US12949488

申请日：2010-11-18

Applicant: Masafumi Ide ,  Toru Takizawa ,  Kaoru Yoda

Inventor： Masafumi Ide ,  Toru Takizawa ,  Kaoru Yoda

IPC: G02F2/02 ,  G02B6/12 ,  H05K3/32 ,  G02B6/42 ,  H05K1/11 ,  G02F1/35 ,  H01S5/022 ,  H05K1/02 ,  H05K1/03

CPC classification number: H05K3/32 ,  G02B6/12007 ,  G02B6/4215 ,  G02B6/4232 ,  G02F2001/3505 ,  H01L24/83 ,  H01L2924/14 ,  H01L2924/351 ,  H01S5/02248 ,  H01S5/02272 ,  H01S5/02276 ,  H05K1/0274 ,  H05K1/0306 ,  H05K1/111 ,  H05K2201/0373 ,  H05K2201/09745 ,  H05K2201/10121 ,  H05K2201/10674 ,  H05K2203/0369 ,  H05K2203/095 ,  Y02P70/611 ,  H01L2924/00

Abstract: An integrated device includes an optical element and an electrical element that are implemented on a substrate. The optical element and the electrical element are bonded by surface-activated bonding technology to a bonding portion that is formed on the substrate and made of metal material.

Abstract translation: 集成器件包括实现在衬底上的光学元件和电子元件。 光学元件和电气元件通过表面激活键合技术结合到形成在基板上并由金属材料制成的接合部分。

公开(公告)号：US09013878B2

公开(公告)日：2015-04-21

申请号：US13626322

申请日：2012-09-25

Applicant: STMicroelectronics S.r.l.

Inventor： Matteo Sebastiano Dimauro ,  Sebastiano Russo ,  Rosalba Cacciola ,  Cristiano Gianluca Stella

IPC: H05K7/20 ,  H05K1/11 ,  H05K3/34

CPC classification number: H05K1/111 ,  H05K3/3431 ,  H05K2201/0373 ,  H05K2201/09663 ,  H05K2201/10166 ,  H05K2201/10969 ,  H05K2203/1178 ,  Y02P70/611 ,  Y02P70/613 ,  Y10T29/49149

Abstract: An electronic system includes an insulating structural element with a coupling surface configured for coupling the electronic system with at least one further electronic system. The electronic system further includes at least one conducting contact element at least partially exposed on the coupling surface. Each conducting contact element has a soldering surface supporting reflow soldering of the conducting contact element with a corresponding further contact element of the further electronic system. In addition, each conducting contact element has at least one lateral surface protruding from the insulating structural element. The soldering surface of the conducting contact element includes at least one channel having an opened end at the protruding lateral surface, the channel configured to facilitate dispersion of waste gas produced during reflow soldering.

Abstract translation: 电子系统包括绝缘结构元件，其具有被配置为将电子系统与至少一个另外的电子系统耦合的耦合表面。 电子系统还包括至少一个至少部分地暴露在耦合表面上的导电接触元件。 每个导电接触元件具有支撑导电接触元件的回流焊接的焊接表面与另外的电子系统的相应的另外的接触元件。 此外，每个导电接触元件具有从绝缘结构元件突出的至少一个侧表面。 导电接触元件的焊接表面包括在突出侧表面具有开口端的至少一个通道，该通道构造成便于在回流焊接期间产生的废气的分散。

公开(公告)号：US08853552B2

公开(公告)日：2014-10-07

申请号：US13314641

申请日：2011-12-08

Applicant: Yoshinori Takenaka ,  Takeshi Nakamura

Inventor： Yoshinori Takenaka ,  Takeshi Nakamura

IPC: H05K1/03 ,  H01L23/498 ,  H05K3/46

CPC classification number: H05K3/465 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L2221/68345 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K2201/0373 ,  H05K2201/0949 ,  H05K2201/09736 ,  H05K2201/10674 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A method for manufacturing a multilayer printed wiring board includes preparing a first resin insulative material having a first conductive circuit on or in the first resin insulative material, forming a second resin insulative material on the first resin insulative material and the first conductive circuit, forming on a surface of the second resin insulative material a first concave portion to be filled with a conductive material for formation of a second conductive circuit, forming on the surface of the second resin insulative material a pattern having a second concave portion and post portions to be filled with the conductive material for formation of a plane conductor, and filling the conductive material in the first concave portion and the second concave portion such that the second conductive circuit and the plane conductor are formed.

Abstract translation: 一种多层印刷电路板的制造方法，其特征在于，在第一树脂绝缘材料上或第一树脂绝缘材料上制备具有第一导电电路的第一树脂绝缘材料，在第一树脂绝缘材料和第一导电电路上形成第二树脂绝缘材料，形成第 所述第二树脂绝缘材料的表面具有要填充用于形成第二导电电路的导电材料的第一凹部，在所述第二树脂绝缘材料的表面上形成具有第二凹部的图案和待填充的柱部分 用于形成平面导体的导电材料，并且在第一凹部和第二凹部中填充导电材料，使得形成第二导电电路和平面导体。

公开(公告)号：US08809687B2

公开(公告)日：2014-08-19

申请号：US13077304

申请日：2011-03-31

Applicant: Hirohito Watanabe

Inventor： Hirohito Watanabe

IPC: H05K1/00 ,  H05K1/03 ,  H05K9/00

CPC classification number: H05K1/028 ,  H05K1/0218 ,  H05K3/1216 ,  H05K2201/0373

Abstract: [Object]To provide a flexible printed board improved in bendability.[Means for solving]The flexible printed board 2 comprises: an insulating substrate 21; a circuit wiring 22 laid on the insulating substrate 21; a circuit protection layer 23 laid on the circuit wiring 22; a shield conductive layer 24 laid on the circuit protection layer 23; and a shield insulating layer 25 laid on the shield conductive layer 24, and is characterized by meeting the following Expression (1). 0.75≦E2/E1≦1.29  Expression (1) Note that E1 denotes the tensile elastic modulus of the shield conductive layer 24 and E2 denotes the tensile elastic modulus of the shield insulating layer 25.

Abstract translation: 提供改善弯曲性的柔性印刷电路板。 [解决方案]柔性印刷电路板2包括：绝缘基板21; 布置在绝缘基板21上的电路布线22; 布置在电路布线22上的电路保护层23; 布置在电路保护层23上的屏蔽导电层24; 以及敷设在屏蔽导电层24上的屏蔽绝缘层25，其特征在于满足下述式（1）。 0.75＆nlE; E2 / E1＆nlE; 1.29表达式（1）注意，E1表示屏蔽导电层24的拉伸弹性模量，E2表示屏蔽绝缘层25的拉伸弹性模量。

公开(公告)号：US08586409B2

公开(公告)日：2013-11-19

申请号：US11662940

申请日：2005-09-29

Applicant: Cécile Davoine ,  Manuel Fendler

Inventor： Cécile Davoine ,  Manuel Fendler

IPC: H01L21/00

CPC classification number: H01L24/13 ,  H01L24/11 ,  H01L24/83 ,  H01L24/90 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/114 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/11474 ,  H01L2224/1148 ,  H01L2224/116 ,  H01L2224/13083 ,  H01L2224/13084 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13155 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/29111 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/83894 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01033 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01057 ,  H01L2924/01058 ,  H01L2924/01067 ,  H01L2924/01079 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/014 ,  H05K3/321 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2201/0373 ,  H05K2201/10977 ,  H05K2203/0278 ,  Y10T29/49126 ,  H01L2224/13099 ,  H01L2924/01082 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A method of electrical connection between a series of hard conductive points and corresponding pads arranged on a one face of a first component, and a series of buried ductile conductive bumps and corresponding pads arranged on one face of a second component. The method comprises forming said series of hard conductive points on said face of the first component; forming said series of buried ductile conducting bumps on said face of the second component; inserting said series of hard conductive points in said series of buried ductile conducting bumps at an ambient temperature; and directly sealing the first and second components together.

Abstract translation: 一系列硬导电点和布置在第一部件的一个面上的对应焊盘之间的电连接的方法，以及布置在第二部件的一个面上的一系列埋地延性导电凸块和相应的焊盘。 该方法包括在第一部件的所述面上形成所述一系列硬导电点; 在所述第二部件的所述面上形成所述一系列埋入的延性传导凸块; 在环境温度下将所述一系列硬导电点插入所述一系列埋地延性传导凸块中; 并将第一和第二部件直接密封在一起。

公开(公告)号：US08466374B2

公开(公告)日：2013-06-18

申请号：US12477146

申请日：2009-06-03

Applicant: Ngai Tsang ,  Kuo-Shu Kao

Inventor： Ngai Tsang ,  Kuo-Shu Kao

IPC: H05K1/00 ,  B05D5/12 ,  B32B38/00 ,  B29C43/20

CPC classification number: H05K3/02 ,  H05K1/0271 ,  H05K1/028 ,  H05K1/118 ,  H05K3/06 ,  H05K3/386 ,  H05K2201/0133 ,  H05K2201/0373 ,  H05K2201/09909

Abstract: A base of circuit board, a circuit board, and a method of fabricating thereof are provided. The circuit board includes a substrate, a plurality of elastic bumps and a patterned circuit layer. The elastic bumps arranged in at least an array are located on the substrate. The patterned circuit layer is located on a portion of the elastic bumps and a portion of the substrate. The base of the circuit board and the method of fabricating thereof are also included in the present invention.

Abstract translation: 提供电路基板，电路板及其制造方法。 电路板包括衬底，多个弹性凸块和图案化电路层。 排列成至少阵列的弹性凸块位于基板上。 图案化电路层位于弹性凸块的一部分和基板的一部分上。 电路基板的基座及其制造方法也包括在本发明中。

公开(公告)号：US08456022B2

公开(公告)日：2013-06-04

申请号：US11817554

申请日：2006-02-09

Applicant: Robert Hammedinger ,  Konrad Kastner ,  Martin Maier ,  Michael Obesser

Inventor： Robert Hammedinger ,  Konrad Kastner ,  Martin Maier ,  Michael Obesser

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H05K1/111 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/0401 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/05559 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/0102 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01051 ,  H01L2924/01057 ,  H01L2924/01061 ,  H01L2924/01068 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/19043 ,  H01L2924/351 ,  H05K3/244 ,  H05K2201/0373 ,  Y02P70/611 ,  Y10T29/49149 ,  H01L2924/00

Abstract: A solderable contact for use with an electrical component includes a pad metallization on a substrate, and an under bump metallization over at least part of the pad metallization. The under bump metallization is in an area for receiving solder. The pad metallization is structured to reveal parts of the substrate surface. The under bump metallization is in direct contact with the parts of the substrate.

Abstract translation: 与电气部件一起使用的可焊接触头包括衬底上的焊盘金属化，以及至少部分焊盘金属化处的凸起下金属化。 凸块下金属化处于用于接收焊料的区域中。 衬垫金属化被构造成露出衬底表面的部分。 底部凸起金属化与衬底的部分直接接触。

公开(公告)号：US08319319B2

公开(公告)日：2012-11-27

申请号：US12235739

申请日：2008-09-23

Applicant: Young-Cheol Jang

Inventor： Young-Cheol Jang

IPC: H01L23/495

CPC classification number: H01L23/3107 ,  H01L23/49503 ,  H01L23/49548 ,  H01L23/49582 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/48095 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01028 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10161 ,  H01L2924/181 ,  H05K3/341 ,  H05K3/3442 ,  H05K2201/0373 ,  H05K2201/10931 ,  Y02P70/613 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor package and mounting method of improving reliability by strengthening adhesive strength of both a printed circuit board and a surface mounting package, includes a chip pad on which a semiconductor device is disposed, and lead terminals, wherein at least one of the chip pad and the lead terminals have a plurality of grooves. Accordingly, in comparison with a typical package, since a plurality of grooves are formed on both a chip pad and lead terminals of a package adhering to a printed circuit, an adhesive area of both the package and the cream solder is widened so that the shearing strength may be improved and greater solder joint reliability can be acquired.

Abstract translation: 通过增强印刷电路板和表面安装封装的粘合强度来提高可靠性的半导体封装和安装方法包括其上设置有半导体器件的芯片焊盘和引线端子，其中芯片焊盘和 引线端子具有多个槽。 因此，与典型的封装相比，由于在附接到印刷电路的封装的芯片焊盘和引线端子上形成多个槽，所以封装和膏状焊料的粘合区域变宽，使得剪切 可以提高强度并且可以获得更大的焊点可靠性。

公开(公告)号：US08274779B2

公开(公告)日：2012-09-25

申请号：US12453635

申请日：2009-05-18

Applicant: Jung Rag Yoon ,  Kyung Min Lee ,  Jeong Woo Han

Inventor： Jung Rag Yoon ,  Kyung Min Lee ,  Jeong Woo Han

IPC: H01G4/06 ,  H01G4/20 ,  H01G4/005 ,  H01G4/38

CPC classification number: H01G4/33 ,  H01G4/01 ,  H01G4/1209 ,  H01G4/1218 ,  H05K1/162 ,  H05K2201/0195 ,  H05K2201/0209 ,  H05K2201/0257 ,  H05K2201/0373 ,  H05K2203/135

Abstract: Provided are an embedded capacitor, an embedded capacitor sheet using the embedded capacitor, and a method of manufacturing the same that may increase a surface area to thereby increase a capacity for each unit area and may provide an embedded capacitor in a sheet to thereby readily lay the embedded capacitor on an embedded printed circuit board. The embedded capacitor may include: a common electrode member 11 including a plurality of grooves 11a; a sealing dielectric layer 12 being formed by sealing a nano dielectric powder with a high dielectric constant in the plurality of grooves 11a formed in the common electrode member 11; a buffer dielectric layer 13 sealing and smoothing an uneven portion of the sealing dielectric layer 12 by applying a paste or a slurry including epoxy of 20 Vol % through 80 Vol % and dielectric powder of 20 Vol % through 80 Vol % with respect to the sealing dielectric layer 12; and an individual electrode member 14 being formed on the buffer dielectric layer 13.

Abstract translation: 提供了嵌入式电容器，使用嵌入式电容器的嵌入式电容器片及其制造方法，其可以增加表面积从而增加每个单位面积的容量，并且可以在片材中提供嵌入式电容器，从而容易地铺设 嵌入式电路板上的嵌入式电容器。 嵌入式电容器可以包括：公共电极构件11，其包括多个槽11a; 密封电介质层12通过在形成在公共电极构件11中的多个槽11a中密封具有高介电常数的纳米介电粉末而形成; 缓冲电介质层13，通过将包含20体积％〜80体积％的环氧树脂的糊剂或包含20体积％〜80体积％的电介质粉末的密封，密封介质层12的不均匀部分密封并平滑， 电介质层12; 以及形成在缓冲介电层13上的单独电极部件14。

公开(公告)号：US08212277B2

公开(公告)日：2012-07-03

申请号：US12510526

申请日：2009-07-28

Applicant: Takaaki Sakai ,  Norifumi Imazeki ,  Soji Owada

Inventor： Takaaki Sakai ,  Norifumi Imazeki ,  Soji Owada

IPC: H01L33/00

CPC classification number: H05K3/325 ,  H01L2224/48091 ,  H01L2924/01327 ,  H01R4/5075 ,  H01R12/7088 ,  H01R13/04 ,  H05K1/056 ,  H05K1/11 ,  H05K2201/0311 ,  H05K2201/0373 ,  H05K2201/10106 ,  H05K2201/10409 ,  H05K2201/10962 ,  H05K2201/2045 ,  H01L2924/00014 ,  H01L2924/00

Abstract: In an optical semiconductor device module constructed by an optical semiconductor device having a light emitting portion on its top surface, a mounting substrate adapted to mount the optical semiconductor device thereon, at least one wiring pattern layer formed on a front surface of the mounting substrate, and at least one power supplying portion in contact with the wiring pattern layer, at least one of the power supplying portion and the wiring pattern layer is uneven.

Abstract translation: 在由其顶表面上具有发光部分的光半导体器件构成的光学半导体器件模块中，适于将光学半导体器件安装在其上的安装衬底，形成在安装衬底的前表面上的至少一个布线图案层， 以及与所述布线图案层接触的至少一个供电部，所述供电部和所述布线图案层中的至少一个是不均匀的。