公开(公告)号：US08298366B2

公开(公告)日：2012-10-30

申请号：US13221358

申请日：2011-08-30

Applicant: Hisayasu Kaneshiro ,  Takashi Kikuchi

Inventor： Hisayasu Kaneshiro ,  Takashi Kikuchi

IPC: B32B37/00 ,  B29C65/00

CPC classification number: H05K1/0346 ,  C09J7/25 ,  C09J2479/086 ,  H05K1/0393 ,  H05K3/386 ,  H05K2201/0154 ,  H05K2201/068 ,  Y10T428/2852 ,  Y10T428/31678

Abstract: Disclosed is an adhesive film having high dimensional stability which can be suitably used for two layer FPCs. Specifically, disclosed is an adhesive sheet composed of an insulating layer and an adhesive layer arranged on one side or both sides of the insulating layer. This adhesive sheet is characterized in that the insulating layer has a ratio E′2/E′1 between the storage elasticity modulus E′1 at 25° C. and the storage elasticity modulus E′2 at 380° C. of not more than 0.2 and a coefficient of thermal expansion in the MD direction of 5-15 ppm at 100-200° C. It is further characterized in that the change in the coefficient of thermal expansion of the adhesive sheet at 100-250° C. after heat treatment at 380° C. for 30 seconds under tension of 20 kg/m is not more than 2.5 ppm in the tension direction and not more than 10 ppm in the direction perpendicular to the tension direction.

Abstract translation: 公开了一种具有高尺寸稳定性的粘合膜，其可以适用于两层FPC。 具体地，公开了由绝缘层和布置在绝缘层的一侧或两侧上的粘合层构成的粘合片。 该粘合片的特征在于绝缘层在25℃下的储能弹性模量E'1与380℃下的储能弹性模量E'2之间的比率E'2 / E'1不大于 0.2，在100〜200℃下MD方向的热膨胀系数为5〜15ppm。其特征还在于，热处理后的粘合片的热膨胀系数在100〜250℃的变化 在拉伸方向下，在380℃，30秒的张力下处理30分钟，在拉伸方向垂直的方向为不大于10ppm。

公开(公告)号：US20120243186A1

公开(公告)日：2012-09-27

申请号：US13492197

申请日：2012-06-08

Applicant: Byung-Nam KIM ,  Heon-Sik SONG ,  Joo-Eun KO ,  Soon-Yong PARK ,  Jung-Jin SHIM

Inventor： Byung-Nam KIM ,  Heon-Sik SONG ,  Joo-Eun KO ,  Soon-Yong PARK ,  Jung-Jin SHIM

IPC: B32B15/08 ,  H05K1/18

CPC classification number: B32B15/08 ,  B32B7/02 ,  B32B15/20 ,  B32B27/08 ,  B32B27/281 ,  B32B2307/51 ,  B32B2457/08 ,  C23C26/00 ,  C23C28/00 ,  H01L23/4985 ,  H01L24/13 ,  H01L24/16 ,  H01L24/80 ,  H01L24/81 ,  H01L2224/16 ,  H01L2224/812 ,  H01L2224/81801 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01055 ,  H01L2924/01067 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H05K1/0346 ,  H05K1/036 ,  H05K3/022 ,  H05K2201/0154 ,  H05K2201/068 ,  Y10T428/24942 ,  Y10T428/2495 ,  Y10T428/266 ,  Y10T428/269 ,  Y10T428/31681

Abstract: The present invention provides a metallic laminate and a method for preparing the same. The metallic laminate includes a metal layer, and at least one polymide resin layer. The polymide resin layer has a modulus of elasticity of 70 Mpa at 400° C.

Abstract translation: 本发明提供一种金属层压体及其制备方法。 金属层压体包括金属层和至少一个聚酰亚胺树脂层。 聚酰亚胺树脂层在400℃下的弹性模量为70Mpa

公开(公告)号：US20120217047A1

公开(公告)日：2012-08-30

申请号：US13407585

申请日：2012-02-28

Applicant: Souhei Kouda ,  Toshiharu Takayama

Inventor： Souhei Kouda ,  Toshiharu Takayama

IPC: H05K1/05

CPC classification number: H05K1/053 ,  H01L23/142 ,  H01L23/49894 ,  H01L2924/0002 ,  H05K3/4685 ,  H05K2201/017 ,  H05K2201/068 ,  H01L2924/00

Abstract: A metal-based circuit board, which reduces the influence of thermal expansion, is provided having a structure where an insulating layer A having a large coefficient of thermal expansion is sandwiched between insulating layers B having a small coefficient of thermal expansion. Such a structure allows the insulating layers B to contract and expand so as to suppress contraction and expansion of the insulating layer A and thereby reduce the stress in the direction of negating the stress. As a result, while warpage or distortion is suppressed to be minimal, the bonding strength of the upper and the lower layer is maintained, and degree of freedom for circuit design is not impaired, thereby providing a highly reliable circuit structure.

Abstract translation: 提供一种减少热膨胀影响的金属基电路板，其具有将具有大的热膨胀系数的绝缘层A夹在具有小的热膨胀系数的绝缘层B之间的结构。 这种结构允许绝缘层B收缩和膨胀，以便抑制绝缘层A的收缩和膨胀，从而减小在否定应力的方向上的应力。 结果，虽然翘曲或变形被抑制到最小，但是上下层的粘合强度得以保持，电路设计的自由度不受损害，从而提供高度可靠的电路结构。

公开(公告)号：US08237057B2

公开(公告)日：2012-08-07

申请号：US12486000

申请日：2009-06-17

Applicant: Takayuki Hirose ,  Norihito Tsukahara ,  Manabu Gokan

Inventor： Takayuki Hirose ,  Norihito Tsukahara ,  Manabu Gokan

IPC: H05K1/09 ,  B05D5/12 ,  B05D3/10 ,  B32B38/14

CPC classification number: H05K3/4602 ,  H05K1/0265 ,  H05K1/0271 ,  H05K1/0272 ,  H05K1/0393 ,  H05K3/1208 ,  H05K3/125 ,  H05K3/205 ,  H05K3/386 ,  H05K3/4069 ,  H05K3/4664 ,  H05K3/4697 ,  H05K2201/0116 ,  H05K2201/0195 ,  H05K2201/0352 ,  H05K2201/0391 ,  H05K2201/068 ,  H05K2201/09036 ,  H05K2201/09136 ,  H05K2201/096 ,  H05K2201/09727 ,  H05K2203/013 ,  H05K2203/0769 ,  Y10S977/773

Abstract: A wiring board is provided that suppresses spreading of liquid droplets when liquid droplets are discharged using an ink-jet method. The wiring board has a plurality of layers and includes an ink-jet wiring pattern that is formed in a soluble porous membrane member of any single layer and that includes electrically conductive nanoparticles as a principal material, and a transferred wiring pattern that does not include electrically conductive nanoparticles as a principal material. One layer among the plurality of layers is an electrically insulative substrate. Another layer among the plurality of layers is a porous membrane treated member layer including a porous membrane member at one part of a region of the other layer. The ink-jet wiring pattern is formed in the porous membrane treated member layer. The transferred wiring pattern is formed in the substrate.

Abstract translation: 提供了一种布线板，其在使用喷墨方法排出液滴时抑制液滴的扩散。 布线板具有多层，并且包括形成在任何单层的可溶性多孔膜构件中并且包括导电纳米颗粒作为主要材料的喷墨布线图案，以及不包括电性的转移布线图案 导电纳米粒子为主要材料。 多层中的一层是电绝缘性基板。 多个层中的另一层是在另一层的一个区域的一部分处具有多孔膜构件的多孔膜处理构件层。 在多孔膜处理构件层中形成喷墨布线图案。 转移的布线图案形成在基板中。

公开(公告)号：US20120168951A1

公开(公告)日：2012-07-05

申请号：US13240083

申请日：2011-09-22

Applicant: Hyun-Ki Kim ,  Dae-Yong Choi ,  Mi-Yeon Kim

Inventor： Hyun-Ki Kim ,  Dae-Yong Choi ,  Mi-Yeon Kim

IPC: H01L23/48 ,  H05K1/09 ,  H05K1/02 ,  H05K1/00

CPC classification number: H05K3/4602 ,  H01L23/49822 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2924/15311 ,  H05K3/4608 ,  H05K2201/068 ,  H05K2201/09136 ,  H01L2924/00

Abstract: Provided are a printed circuit board (PCB) and a semiconductor package including the same. The PCB includes a core layer having a stacked structure including at least a first layer made of a first material that has a first coefficient of thermal expansion (CTE) and a second layer made of a second material that has a second CTE different from the first CTE, an upper wiring layer disposed on a first surface of the core layer, and a lower wiring layer disposed on a second surface of the core layer opposite the first surface.

Abstract translation: 提供了一种印刷电路板（PCB）和包括其的半导体封装。 PCB包括具有层叠结构的芯层，该堆叠结构至少包括由具有第一热膨胀系数（CTE）的第一材料制成的第一层和由具有第二CTE的第二材料制成的第二层，第二层具有不同于第一 CTE，设置在芯层的第一表面上的上布线层和布置在与第一表面相对的芯层的第二表面上的下布线层。

公开(公告)号：US08209859B2

公开(公告)日：2012-07-03

申请号：US12123733

申请日：2008-05-20

Applicant: Louis H. Feinstein

Inventor： Louis H. Feinstein

IPC: H05K3/30

CPC classification number: H05K3/284 ,  H05K2201/068 ,  H05K2201/0769 ,  H05K2201/09909 ,  H05K2201/10636 ,  H05K2201/10977 ,  H05K2203/0126 ,  Y02P70/611 ,  Y10T29/4913 ,  Y10T29/49146 ,  Y10T29/49171 ,  Y10T29/49227 ,  Y10T29/52 ,  Y10T29/53087 ,  Y10T29/53174 ,  Y10T29/53178

Abstract: A technique for processing an electronic apparatus (e.g., manufacturing an assembled circuit board, treating an assembled circuit board, etc.) involves applying encasement material to an area of the circuit board assembly while leaving at least a portion of the circuit board assembly exposed. The technique further involves causing the applied encasement material to harden (e.g., heating the encasement material in a curing oven, applying radiation, providing a chemical catalyst, etc.). Application and hardening of the encasement material may take place shortly after circuit board assembly (e.g., by automated equipment at a manufacturing facility in order to treat newly assembled boards) or at some later time in the field (e.g., by a technician servicing a legacy board).

Abstract translation: 一种用于处理电子设备（例如，制造组装电路板，处理组装电路板等）的技术涉及将外壳材料施加到电路板组件的区域，同时使电路板组件的至少一部分露出。 该技术还包括使所施加的包装材料硬化（例如，在固化炉中加热包装材料，施加辐射，提供化学催化剂等）。 封装材料的应用和硬化可能在电路板组装之后不久（例如，通过制造设施处的自动化设备来处理新组装的板）或在现场的某个稍后的时间（例如，由维护遗留物的技术人员） 板）。

公开(公告)号：US08183469B2

公开(公告)日：2012-05-22

申请号：US12348514

申请日：2009-01-05

Applicant: Masahiro Sunohara ,  Kei Murayama ,  Takaharu Yamano

Inventor： Masahiro Sunohara ,  Kei Murayama ,  Takaharu Yamano

IPC: H05K1/11

CPC classification number: H05K3/4092 ,  H01L2224/05567 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81141 ,  H01L2924/01322 ,  H05K3/062 ,  H05K3/326 ,  H05K3/4007 ,  H05K2201/0311 ,  H05K2201/0338 ,  H05K2201/068 ,  H05K2201/1059 ,  H05K2201/10674 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A wiring board includes an external connection terminal of a cylindrical shape, in which an electrode terminal of the electronic component to be mounted is fitted. In one configuration, a portion of the external connection terminal is electrically connected to a pad portion formed on an electronic component mounting surface side of the wiring board, and the external connection terminal is curvedly formed in such a shape that the outer periphery of the electrode terminal comes into close contact with the inner periphery of the middle portion of the external connection terminal when the electrode terminal is inserted into the external connection terminal.

Abstract translation: 布线基板包括一个圆柱形外部连接端子，其中安装有电子元件的电极端子。 在一种构造中，外部连接端子的一部分电连接到形成在布线板的电子部件安装表面侧上的焊盘部分，并且外部连接端子被弯曲地形成为使得电极的外周 当电极端子插入外部连接端子时，端子与外部连接端子的中部的内周紧密接触。

公开(公告)号：US20120113608A1

公开(公告)日：2012-05-10

申请号：US13292630

申请日：2011-11-09

Applicant: Mohan R. Nagar ,  Kuo-Chuan Liu ,  Mudasir Ahmad ,  Bangalore J. Shanker ,  Jie Xue

Inventor： Mohan R. Nagar ,  Kuo-Chuan Liu ,  Mudasir Ahmad ,  Bangalore J. Shanker ,  Jie Xue

IPC: H05K7/06 ,  H05K3/34

CPC classification number: H05K1/0271 ,  H01L21/563 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10253 ,  H05K1/181 ,  H05K3/305 ,  H05K2201/068 ,  H05K2201/09036 ,  H05K2201/10674 ,  H05K2201/10977 ,  Y02P70/613 ,  Y10T29/49144 ,  H01L2924/00 ,  H01L2224/0401

Abstract: A printed circuit board assembly and method of assembly in which underfill is placed between a chip and substrate to support the chip. A trench is formed in the upper layer of the printed circuit board to limit the flow of the underfill and in particular to limit the underfill from contact with adjacent components so that the underfill does not interfere with adjacent components on the printed circuit board assembly.

Abstract translation: 一种印刷电路板组件和组装方法，其中将底部填充物放置在芯片和基板之间以支撑芯片。 沟槽形成在印刷电路板的上层中以限制底部填充物的流动，特别是限制底部填充物与相邻部件的接触，使得底部填充物不会干扰印刷电路板组件上的相邻部件。

公开(公告)号：US20120098137A1

公开(公告)日：2012-04-26

申请号：US13381299

申请日：2010-06-30

Applicant: Ryosuke Usui ,  Yusuke Igarashi ,  Yasunori Inoue ,  Mayumi Nakasato ,  Masayuki Nagamatsu ,  Yasuhiro Kohara

Inventor： Ryosuke Usui ,  Yusuke Igarashi ,  Yasunori Inoue ,  Mayumi Nakasato ,  Masayuki Nagamatsu ,  Yasuhiro Kohara

IPC: H01L29/43 ,  H01L23/48 ,  H05K7/20

CPC classification number: H05K3/445 ,  H01L23/3735 ,  H01L24/48 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/181 ,  H05K1/05 ,  H05K1/053 ,  H05K1/056 ,  H05K1/185 ,  H05K2201/0195 ,  H05K2201/068 ,  H01L2924/00015 ,  H01L2224/05599 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Conventional printed circuit boards had a problem of being inferior in heat-radiation characteristic, and metal-core printed circuit boards adopted to improve the heat-radiation characteristic had problems in having low rigidity and a tendency to bend. The ductility of the metal can be obstructed, and the metal protected; by covering substantially the whole area of the front and back sides of the metal core, consisting of metal as the main material, with a first ceramic film and a second ceramic film that obstruct the ductility of the aforementioned metal-core; and covering each of the ceramic films with insulated resin films, to cover the fragility of these ceramics.

Abstract translation: 传统的印刷电路板具有热辐射特性差的问题，并且用于改善热辐射特性的金属芯印刷电路板具有刚性低和弯曲倾向的问题。 金属的延展性可能受到阻碍，金属受到保护; 通过覆盖由金属作为主要材料构成的金属芯的正面和背面的大部分整个面积与第一陶瓷膜和阻碍上述金属芯的延展性的第二陶瓷膜; 并用绝缘树脂膜覆盖每个陶瓷膜，以覆盖这些陶瓷的脆性。

公开(公告)号：US08163381B2

公开(公告)日：2012-04-24

申请号：US12256665

申请日：2008-10-23

Applicant: Pui-Yan Lin ,  Govindasamy Paramasivam Rajendran ,  George Elias Zahr

Inventor： Pui-Yan Lin ,  Govindasamy Paramasivam Rajendran ,  George Elias Zahr

IPC: H05K1/02

CPC classification number: H01L23/49894 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/0271 ,  H05K3/108 ,  H05K3/4661 ,  H05K2201/0209 ,  H05K2201/0269 ,  H05K2201/068 ,  Y10T29/49126 ,  Y10T29/49156 ,  Y10T29/49165 ,  Y10T428/24917 ,  Y10T428/25 ,  Y10T428/2998 ,  Y10T428/31515 ,  Y10T428/31518 ,  Y10T428/31529 ,  H01L2924/00

Abstract: Provided, are multi-layer chip carriers comprising an asymmetric cross-linked polymeric dielectric film, and processes for making the chip carriers.

Abstract translation: 提供了包括不对称交联聚合物电介质膜的多层芯片载体，以及用于制造芯片载体的工艺。