公开(公告)号：US07550826B2

公开(公告)日：2009-06-23

申请号：US11702971

申请日：2007-02-06

Applicant: Kelly M. Orth ,  Chad M. McGuire

Inventor： Kelly M. Orth ,  Chad M. McGuire

IPC: H01L23/552

CPC classification number: H05K9/0049 ,  H01L2224/48091 ,  H05K1/0215 ,  H05K1/0218 ,  H05K1/112 ,  H05K7/1462 ,  H05K9/0052 ,  H05K2201/0723 ,  H05K2201/09536 ,  H05K2201/09627 ,  H05K2201/10151 ,  H01L2924/00014

Abstract: A field hardened industrial device is described with a housing of the device having electrically conductive walls surrounding a cavity with an open end. An electronics assembly is adapted to fit within the cavity. The device includes a circuit card assembly, which is a multi-layered printed wiring board with pass-through electrical connections and an embedded ground plane electrically coupled to the housing to shield the electronics assembly from electromagnetic interference and to provide environmental protection to the electronics assembly.

Abstract translation: 描述了一种场强淬火的工业装置，该装置的壳体具有围绕具有开口端的空腔的导电壁。 电子组件适于装配在腔内。 该装置包括电路卡组件，其是具有通过电连接的多层印刷布线板和电耦合到壳体的嵌入式接地平面，以屏蔽电子组件免受电磁干扰并向电子组件提供环境保护 。

公开(公告)号：US20090140400A1

公开(公告)日：2009-06-04

申请号：US11949329

申请日：2007-12-03

Applicant: Daniel Irwin Amey, JR. ,  William Borland

Inventor： Daniel Irwin Amey, JR. ,  William Borland

IPC: H01L23/48 ,  H01L21/50

CPC classification number: H05K1/162 ,  H01L2224/16225 ,  H05K1/112 ,  H05K3/429 ,  H05K3/4602 ,  H05K2201/09536 ,  H05K2201/09763 ,  H05K2201/10674

Abstract: A printed wiring board semiconductor package or PWB power core comprising singulated capacitors embedded on multiple layers of the printed wiring board semiconductor package wherein at least a part of each embedded capacitor lies within the die shadow and wherein the embedded, singulated capacitors comprise at least a first electrode and a second electrode. The first electrodes and second electrodes of the embedded singulated capacitors are interconnected to the Vcc (power) terminals and the Vss (ground) terminals respectively of a semiconductor device. The size of the embedded capacitors are varied to produce different self-resonant frequencies and their vertical placements within the PWB semiconductor package are used to control the inherent inductance of the capacitor-semiconductor electrical interconnections so that customized resonant frequencies of the embedded capacitors can be achieved with low impedance.

Abstract translation: 一种印刷线路板半导体封装或PWB功率核，其包括嵌入在所述印刷线路板半导体封装的多层上的单片电容器，其中每个嵌入式电容器的至少一部分位于所述管芯阴影内，并且其中所述嵌入式单片电容器包括至少第一 电极和第二电极。 嵌入式单片电容器的第一电极和第二电极分别与半导体器件的Vcc（功率）端子和Vss（接地）端子互连。 嵌入式电容器的尺寸变化以产生不同的自谐振频率，并且它们在PWB半导体封装内的垂直布置用于控制电容器 - 半导体电互连的固有电感，从而可以实现嵌入式电容器的定制谐振频率 具有低阻抗。

公开(公告)号：US20090126983A1

公开(公告)日：2009-05-21

申请号：US11942061

申请日：2007-11-19

Applicant: Paul M. Harvey ,  Douglas O. Powell ,  Wolfgang Sauter ,  Yaping Zhou

Inventor： Paul M. Harvey ,  Douglas O. Powell ,  Wolfgang Sauter ,  Yaping Zhou

IPC: H05K1/02 ,  H05K3/10

CPC classification number: H05K1/115 ,  H05K1/0233 ,  H05K1/112 ,  H05K3/42 ,  H05K3/4602 ,  H05K2201/086 ,  H05K2201/09536 ,  H05K2201/096

Abstract: A method, system and apparatus for coating plated through holes (PTHs) to reduce impedance discontinuity in electronic packages. PTH vias are imbedded in the core of a printed circuit board comprising a core layer, a plurality of buildup layers, a plurality of micro-vias, and a plurality of traces. Traces electrically interconnect each of the micro-vias to PTH vias, forming an electrically conductive path. PTHs are coated with a magnetic metal material, such as nickel, to increase the internal and external conductance of the PTHs, thereby providing decreased impedance discontinuity of the signals in electronic packages.

Abstract translation: 一种用于涂覆电镀通孔（PTH）的方法，系统和装置，以减少电子封装中的阻抗不连续性。 PTH通孔嵌入印刷电路板的芯中，该印刷电路板包括芯层，多个堆积层，多个微通孔和多个迹线。 迹线将每个微通孔电连接到PTH通孔，形成导电路径。 PTH用诸如镍的磁性金属材料涂覆以增加PTH的内部和外部电导，从而在电子封装中提供信号的阻抗不连续性。

公开(公告)号：US20090091406A1

公开(公告)日：2009-04-09

申请号：US12249273

申请日：2008-10-10

Applicant: Taras KUSHTA ,  Kaoru Narita ,  Takanori Saeki ,  Tomoyuki Kaneko ,  Hirokazu Tohya

Inventor： Taras KUSHTA ,  Kaoru Narita ,  Takanori Saeki ,  Tomoyuki Kaneko ,  Hirokazu Tohya

IPC: H01P1/00

CPC classification number: H05K1/0222 ,  H01P3/06 ,  H05K1/024 ,  H05K1/0251 ,  H05K3/429 ,  H05K2201/0187 ,  H05K2201/09063 ,  H05K2201/09536 ,  H05K2201/09618 ,  H05K2201/09718 ,  H05K2201/09809

Abstract: A compact via transmission line for a printed circuit board having preferred characteristic impedance and capable of miniaturizing the printed circuit board including a multilayer printed circuit board, and extending the frequency range of a via transmission line mounted on the printed circuit board, and a design method of the same. The transmission line has a central conductor forming an inner conductor layer boundary make up a signal via hole, a plurality of via holes arranged around the central conductor form an outer conductor layer boundary, and a plurality of conductor plates formed of a printed circuit board conductor layer, is further provided with a constitutive parameter adjustment clearance hole between the inner and outer conductor layer boundaries of the compact via transmission line, and electrically isolates to prevent cross-talk of a signal propagating through a signal via hole with other signals in a high-frequency signal band.

Abstract translation: 一种用于具有优选特性阻抗并能够使包括多层印刷电路板的印刷电路板小型化并且扩展安装在印刷电路板上的通孔传输线的频率范围的印刷电路板的紧凑型通路传输线，以及设计方法 一样的。 传输线具有形成内导体层边界的中心导体，构成信号通孔，围绕中心导体布置的多个通孔形成外导体层边界，以及由印刷电路板导体形成的多个导体板 通过传输线在压缩体的内部和外部导体层边界之间进一步设置本构参数调整间隙孔，并且电隔离以防止通过信号通孔传播的信号与其他信号在高电平中的串扰 频率信号频带。

公开(公告)号：US20090080168A1

公开(公告)日：2009-03-26

申请号：US12199489

申请日：2008-08-27

Applicant: Shigeru SUGINO

Inventor： Shigeru SUGINO

IPC: H05K1/18 ,  H05K3/30

CPC classification number: H05K3/4046 ,  H01L2224/16227 ,  H05K1/023 ,  H05K1/113 ,  H05K1/184 ,  H05K1/186 ,  H05K3/0047 ,  H05K3/321 ,  H05K3/462 ,  H05K3/4623 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2201/10454 ,  H05K2201/10636 ,  H05K2201/10734 ,  H05K2203/0242 ,  H05K2203/063 ,  Y02P70/611 ,  Y10T29/4913

Abstract: A printed circuit board includes a mounted a first electronic component. The printed circuit board includes a first through holes extending from a mounting surface on which the electronic component is mounted The printed circuit board includes a second through holes extending from a surface opposite the mounting surface and aligned with the first through holes. A second electronic component may be longitudinally between the first through holes and the second through holes. The first and second through holes may be electrically connected with the second electronic component.

Abstract translation: 印刷电路板包括安装的第一电子部件。 印刷电路板包括从其上安装电子部件的安装表面延伸的第一通孔。印刷电路板包括从与安装表面相对的表面延伸并与第一通孔对准的第二通孔。 第二电子部件可以在第一通孔和第二通孔之间纵向延伸。 第一和第二通孔可以与第二电子部件电连接。

公开(公告)号：US07507913B2

公开(公告)日：2009-03-24

申请号：US10522335

申请日：2003-03-24

Applicant: Yasushi Inagaki ,  Katsuyuki Sano

Inventor： Yasushi Inagaki ,  Katsuyuki Sano

IPC: H05K1/16

CPC classification number: H05K1/09 ,  H01L23/49816 ,  H01L23/49822 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01025 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/19106 ,  H01L2924/3011 ,  H01L2924/3511 ,  H05K1/0237 ,  H05K1/056 ,  H05K1/183 ,  H05K1/185 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4608 ,  H05K3/4641 ,  H05K2201/0347 ,  H05K2201/0352 ,  H05K2201/09309 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/09809 ,  H01L2224/05599

Abstract: A package substrate free of malfunction or error even with an IC chip in a high frequency range, particularly an IC chip with a frequency exceeding 3 GHz, is provided. A conductor layer 34P on a core substrate 30 is formed to have a thickness of 30 μm and a conductor circuit 58 on an interlayer resin insulating layer 50 is formed to have a thickness of 15 μm. By making the conductor layer 34P thick, it is possible to increase a volume of the conductor itself and decrease resistance. Further, by employing the conductor layer 34 as a power supply layer, it is possible to improve a capability of supplying power to the IC chip.

Abstract translation: 即使IC芯片处于高频范围，特别是具有频率超过3GHz的IC芯片，也不会出现故障或误差的封装基板。 芯基板30上的导体层34P形成为具有30μm的厚度，层间树脂绝缘层50上的导体电路58形成为15μm的厚度。 通过使导体层34P变厚，可以增加导体本身的体积并降低电阻。 此外，通过使用导体层34作为电源层，可以提高向IC芯片供电的能力。

公开(公告)号：US20090056998A1

公开(公告)日：2009-03-05

申请号：US11848330

申请日：2007-08-31

Applicant: Roger A. Booth, Jr. ,  John R. Dangler ,  Matthew S. Doyle ,  Jesse Hefner ,  Thomas W. Liang ,  Ankur K. Patel ,  Paul Rudrud

Inventor： Roger A. Booth, Jr. ,  John R. Dangler ,  Matthew S. Doyle ,  Jesse Hefner ,  Thomas W. Liang ,  Ankur K. Patel ,  Paul Rudrud

IPC: H05K1/11 ,  H05K3/10

CPC classification number: H05K3/429 ,  H05K1/0222 ,  H05K1/115 ,  H05K2201/09536 ,  H05K2201/09809 ,  H05K2203/061 ,  Y10T29/49165

Abstract: Disclosed herein is a method comprising drilling a first hole in a multilayered device; the multilayered device comprising a fill layer disposed between and in intimate contact with two layers of a first electrically conducting material; the fill layer being electrically insulating; plating the first hole with a slurry; the slurry comprising a magnetic material, an electrically conducting material, or a combination comprising at least one of the foregoing materials; filling the first hole with a fill material; the fill material being electrically insulating; laminating a first layer and a second layer on opposing faces of the multilayered device to form a laminate; the opposing faces being the faces through which the first hole is drilled; the first layer and the second layer each comprising a second electrically conducting material; drilling a second hole through the laminate; the second hole having a circumference that is encompassed by a circumference of the first hole; and plating the surface of the second hole with a third electrically conducting material.

Abstract translation: 本文公开了一种方法，包括在多层装置中钻出第一孔; 所述多层器件包括设置在两层第一导电材料之间并与之紧密接触的填充层; 填充层电绝缘; 用浆料电镀第一个孔; 所述浆料包括磁性材料，导电材料或包含至少一种前述材料的组合; 用填充材料填充第一个孔; 填充材料电绝缘; 在所述多层器件的相对面上层叠第一层和第二层以形成层压体; 相对的面是钻出第一孔的面; 所述第一层和所述第二层各自包括第二导电材料; 穿过层压板钻出第二个孔; 所述第二孔具有由所述第一孔的圆周包围的圆周; 以及用第三导电材料电镀所述第二孔的表面。

公开(公告)号：US20090056118A1

公开(公告)日：2009-03-05

申请号：US12262261

申请日：2008-10-31

Applicant: Roger CHANG

Inventor： Roger CHANG

IPC: H05K3/30

CPC classification number: H05K1/187 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/5389 ,  H01L24/48 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/16195 ,  H01L2924/1627 ,  H01L2924/19041 ,  H01L2924/19043 ,  H05K1/186 ,  H05K3/28 ,  H05K3/4623 ,  H05K3/4652 ,  H05K2201/0358 ,  H05K2201/09536 ,  H05K2201/10674 ,  H05K2203/063 ,  H05K2203/068 ,  H05K2203/085 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49146 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2224/85 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/0401 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A method has acts of providing at least two multilayer circuit boards, combining the at least two multilayer circuit boards to form a combined multilayer circuit board, forming multiple outer conductive vias, circuits and contacts on the combined multilayer circuit board. Each multilayer circuit board is fabricated by steps of preparing a single-layer printed circuit board having multiple chip sections, attaching at least one chip to the corresponding chip section, attaching a frame having multiple enclosures to the single-layer printed circuit board, attaching a semi-fluid glue sheet to the frame, vacuum pressing a conductive layer on the semi-fluid glue sheet and forming multiple conductive inner vias through the multilayer circuit board. The at least two multilayer circuit boards are combined by steps of reversing one of the multilayer circuit boards and vacuum pressing other multilayer circuit boards on the reversed multilayer circuit board.

Abstract translation: 一种方法具有提供至少两个多层电路板的动作，组合至少两个多层电路板以形成组合的多层电路板，在组合的多层电路板上形成多个外部导电通孔，电路和触点。 每个多层电路板通过制备具有多个芯片部分的单层印刷电路板的步骤制造，将至少一个芯片附接到相应的芯片部分，将具有多个外壳的框架附接到单层印刷电路板， 半流体胶片到框架，真空挤压半流体胶片上的导电层，并通过多层电路板形成多个导电内通孔。 所述至少两个多层电路板通过反转多层电路板中的一个并在反向多层电路板上真空压制其它多层电路板的步骤组合。

公开(公告)号：US07490402B2

公开(公告)日：2009-02-17

申请号：US11902758

申请日：2007-09-25

Applicant: Deepak K. Pai ,  Ronald R. Denny

Inventor： Deepak K. Pai ,  Ronald R. Denny

IPC: H05K3/36 ,  B23K31/00

CPC classification number: H05K3/462 ,  H01L2224/05548 ,  H05K3/28 ,  H05K3/3463 ,  H05K3/3484 ,  H05K3/4623 ,  H05K2201/0305 ,  H05K2201/0347 ,  H05K2201/0949 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2203/043 ,  H05K2203/063 ,  H05K2203/0733 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49147 ,  Y10T29/49149 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T29/49213

Abstract: The present invention provides a number of techniques for laminating and interconnecting multiple substrates to form a multilayer package or other circuit component. A solder bump may be formed on the conductive pad of at least one of two or more substrates. The solder bump preferably is formed from an application of solder paste to the conductive pad(s). Adhesive films may be positioned between the surfaces of the substrates having the conductive pads, where the adhesive films include apertures located substantially over the conductive pads such that the conductive pads and/or solder bumps confront each other through the aperture. The two or more substrates then may be pressed together to mechanically bond the two or more substrates via the adhesive films. The solder bump(s) may be reflowed during or after the lamination to create a solder segment that provides an electrical connection between the conductive pads through the aperture in the adhesive films.

Abstract translation: 本发明提供了用于层叠和互连多个基板以形成多层封装或其他电路部件的多种技术。 可以在两个或更多个基板中的至少一个的导电焊盘上形成焊料凸块。 焊料凸块优选地由焊膏应用于导电焊盘形成。 粘合剂膜可以位于具有导电焊盘的基板的表面之间，其中粘合剂膜包括基本上位于导电焊盘上方的孔，使得导电焊盘和/或焊料凸块通过孔彼此面对。 然后可以将两个或更多个基底压在一起以经由粘合剂膜机械地粘合两个或更多个基底。 可以在叠层期间或之后回流焊料凸块以产生焊接段，该焊料段通过粘合剂膜中的孔提供导电焊盘之间的电连接。

公开(公告)号：US20090000812A1

公开(公告)日：2009-01-01

申请号：US12163286

申请日：2008-06-27

Applicant: Takashi KARIYA

Inventor： Takashi KARIYA

IPC: H05K1/16 ,  H05K3/30

CPC classification number: H01L23/49838 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/16225 ,  H01L2224/16227 ,  H05K1/113 ,  H05K1/115 ,  H05K3/4602 ,  H05K3/4652 ,  H05K2201/0352 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2201/10674 ,  Y10T29/49139

Abstract: A multilayer printed wiring board includes a core substrate and a built-up wiring layer formed by alternately layering conductor circuits and insulating resin layers. The built-up wiring layer includes a first surface provided in contact with the core substrate and a second surface opposing the first surface and including a mounting area on which at least one semiconductor device is to be mounted. A first plurality of through-hole conductors is formed in a first portion of the core substrate which corresponds to the mounting area of the second surface, and a second plurality of through-hole conductors formed in a second portion of the core substrate which corresponds to another area of the second surface other than the mounting area. A pitch between the first plurality of through-hole conductors is smaller than a pitch between the second plurality of through-hole conductors. In one aspect, a ratio of pads to through holes directly below a processor core section of the semiconductor device is less that a number of pads to through holes in an area outside the processor core.

Abstract translation: 多层印刷电路板包括芯基板和通过交替层叠导体电路和绝缘树脂层而形成的积层布线层。 所述积层布线层包括与所述芯基板接触的第一表面和与所述第一表面相对的第二表面，并且包括将要安装至少一个半导体器件的安装区域。 第一多个通孔导体形成在芯基板的与第二表面的安装区域对应的第一部分中，第二多个通孔导体形成在芯基板的第二部分中，其对应于 第二表面的另一区域，而不是安装区域。 第一多个通孔导体之间的间距小于第二多个通孔导体之间的节距。 在一个方面，焊盘与半导体器件的处理器核心部分正下方的通孔的比例小于处理器核心外部区域中通孔的数量。