公开(公告)号：US08389398B2

公开(公告)日：2013-03-05

申请号：US13431816

申请日：2012-03-27

Applicant: KiYoun Jang ,  SungSoo Kim ,  YongHee Kang

Inventor： KiYoun Jang ,  SungSoo Kim ,  YongHee Kang

IPC: H01L21/44

CPC classification number: H01L23/49811 ,  H01L21/4846 ,  H01L21/6835 ,  H01L23/498 ,  H01L23/49827 ,  H01L24/06 ,  H01L2221/68359 ,  H01L2221/68363 ,  H01L2224/0401 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30105 ,  H05K3/108 ,  H05K3/205 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2201/0376 ,  H05K2201/097 ,  H05K2201/09736 ,  H05K2203/049 ,  H05K2203/1476 ,  H01L2924/00

Abstract: A method of making a semiconductor device comprises providing a carrier, forming a first conductive layer extending above a surface of the carrier, providing a substrate, disposing the first conductive layer into a first surface of the substrate, removing the carrier, forming a second conductive layer extending above the first surface of the substrate to create a vertical offset between the first conductive layer and second conductive layer, and forming a plurality of first bumps over the first conductive layer and second conductive layer. The method further includes the steps of disposing a third conductive layer into a second surface of the substrate opposite the first surface of the substrate, forming a fourth conductive layer extending above the second surface of the substrate to create a vertical offset between the third conductive layer and fourth conductive layer, and forming a plurality of second bumps.

Abstract translation: 制造半导体器件的方法包括提供载体，形成在载体的表面上延伸的第一导电层，提供衬底，将第一导电层设置在衬底的第一表面中，去除载体，形成第二导电 层，其在所述基板的所述第一表面上方延伸以在所述第一导电层和所述第二导电层之间产生垂直偏移，以及在所述第一导电层和所述第二导电层上形成多个第一凸块。 该方法还包括以下步骤：将第三导电层设置在与衬底的第一表面相对的衬底的第二表面中，形成在衬底的第二表面之上延伸的第四导电层，以在第三导电层 和第四导电层，并形成多个第二凸块。

公开(公告)号：US20130002387A1

公开(公告)日：2013-01-03

申请号：US13173022

申请日：2011-06-30

Applicant: Chih-Ming Kuo ,  You-Ming Hsu

Inventor： Chih-Ming Kuo ,  You-Ming Hsu

IPC: H01F5/00 ,  H05K3/10

CPC classification number: H01F5/00 ,  H01F5/003 ,  H05K1/165 ,  H05K3/465 ,  H05K2201/097 ,  Y10T29/4902 ,  Y10T29/49069 ,  Y10T29/49071 ,  Y10T29/49073 ,  Y10T29/49155

Abstract: A method for fabricating a carrier with a three-dimensional inductor comprises the steps of providing a substrate having a protective layer; forming a first photoresist layer on the protective layer; patterning the first photoresist layer to form a second opening and a plurality of disposing slots; forming a first metal layer in second opening and disposing slots; removing the first photoresist layer; forming a first dielectric layer on the protective layer; forming a second photoresist layer on the first dielectric layer; patterning the second photoresist layer to form a plurality of slots; forming a second metal layer in slots to form a plurality of inductive portions; removing the second photoresist layer; forming a second dielectric layer on the first dielectric layer; forming a third photoresist layer on the second dielectric layer; patterning the third photoresist layer to form a plurality of slots; and forming a third metal layer in slots.

公开(公告)号：US20120181704A1

公开(公告)日：2012-07-19

申请号：US13420341

申请日：2012-03-14

Applicant: Frank Lambrecht

Inventor： Frank Lambrecht

IPC: H01L23/48 ,  H01L21/60

CPC classification number: H01L23/48 ,  G11C5/025 ,  G11C5/04 ,  G11C7/1057 ,  G11C7/1084 ,  H01L25/18 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/181 ,  H05K2201/097 ,  H05K2201/10159 ,  H05K2203/1572 ,  Y02P70/611 ,  H01L2924/00

Abstract: The semiconductor module includes a plurality of memory die on a first side of a substrate and a plurality of buffer die on a second side of the substrate. Each of the memory die is disposed opposite and electrically coupled to one of the buffer die.

Abstract translation: 半导体模块包括在衬底的第一侧上的多个存储器管芯和在衬底的第二侧上的多个缓冲管芯。 每个存储器管芯相对设置并电耦合到缓冲管芯之一。

公开(公告)号：US20120170231A1

公开(公告)日：2012-07-05

申请号：US13198370

申请日：2011-08-04

Applicant: Baik-Woo LEE

Inventor： Baik-Woo LEE

IPC: H05K1/18 ,  H05K3/20

CPC classification number: H05K1/145 ,  H01L21/568 ,  H01L24/24 ,  H01L24/82 ,  H01L24/96 ,  H01L2224/04105 ,  H01L2224/24137 ,  H01L2224/82031 ,  H01L2224/82039 ,  H01L2924/14 ,  H05K1/028 ,  H05K1/147 ,  H05K1/185 ,  H05K1/189 ,  H05K2201/055 ,  H05K2201/056 ,  H05K2201/097 ,  Y10T29/49128 ,  H01L2924/00

Abstract: A folded stacked package and a method of manufacturing the same are provided. The folded stacked package includes a flexible board or substrate comprising first, second and third device packaging units, and first and second folding unit units. The flexible board has wiring patterns formed thereon; one or more active devices disposed in at least one of the first, second, and third device packaging units; and one or more passive devices disposed on a surface of each of the first and second device packaging units. The passive devices include one or more first passive devices disposed on the surface of the first device packaging unit and one or more second passive devices disposed on the surface of the second device packaging unit. The first and second passive devices do not overlap each other when the flexible board is folded at the folding unit.

Abstract translation: 提供折叠的堆叠包装及其制造方法。 折叠的堆叠包装包括包括第一，第二和第三装置包装单元以及第一和第二折叠单元单元的柔性板或基板。 柔性板具有形成在其上的布线图案。 设置在所述第一，第二和第三装置包装单元中的至少一个中的一个或多个有源装置; 以及设置在每个第一和第二装置包装单元的表面上的一个或多个无源装置。 无源器件包括设置在第一器件封装单元的表面上的一个或多个第一无源器件和设置在第二器件封装单元的表面上的一个或多个第二无源器件。 当柔性板在折叠单元处折叠时，第一和第二被动装置彼此不重叠。

公开(公告)号：US20110278951A1

公开(公告)日：2011-11-17

申请号：US13194383

申请日：2011-07-29

Applicant: Takeshi KURIHARA ,  Keiichi ICHIKAWA

Inventor： Takeshi KURIHARA ,  Keiichi ICHIKAWA

IPC: H01F38/14

CPC classification number: H02J50/10 ,  H01F38/14 ,  H02J5/005 ,  H02J7/025 ,  H02J50/12 ,  H02J50/70 ,  H05K1/0216 ,  H05K1/0265 ,  H05K1/115 ,  H05K2201/0792 ,  H05K2201/09627 ,  H05K2201/097 ,  H05K2201/0979 ,  H05K2201/1003 ,  H05K2201/10166

Abstract: The disclosure provides a non-contact power receiving apparatus including a conductive pattern in a second region of a substrate not covered by a magnetic sheet. The conductive pattern includes first and second electrodes provided in a first plane parallel to a surface of the substrate and arranged in a length direction of the conductive pattern. A third electrode is formed on a second plane parallel with the first plane. A first via hole connects superposed portions of the first and third electrodes to each other, and a second via hole connects superposed portions of the second and third electrodes to each other. As a result, loops of eddy currents generated in the conductive pattern can be made to be small, whereby eddy current loss can be reduced.

Abstract translation: 本公开提供一种非接触式电力接收装置，其包括在未被磁性片覆盖的基板的第二区域中的导电图案。 导电图案包括设置在与基板的表面平行的第一平面中并沿导电图案的长度方向布置的第一和第二电极。 第三电极形成在与第一平面平行的第二平面上。 第一通孔将第一和第三电极的叠置部彼此连接，第二通孔将第二电极和第三电极的叠置部彼此连接。 结果，可以使在导电图案中产生的涡流的回路小，从而可以减小涡流损耗。

公开(公告)号：US08031033B2

公开(公告)日：2011-10-04

申请号：US11605253

申请日：2006-11-29

Applicant: Barry Mansell ,  Gail E. Mansell, legal representative

Inventor： Barry Mansell

IPC: H01P1/18

CPC classification number: H05K1/165 ,  H01F17/0033 ,  H01F17/02 ,  H05K1/0237 ,  H05K2201/097 ,  Y10T477/6895

Abstract: A printed solenoid inductor delay line system comprises discrete delay sections, where the inductor is implemented in the form of a printed, spiraling solenoid, with the solenoid axis in the plane of the multi-layer printed circuit board (PCB).

Abstract translation: 印刷电磁线圈电感器延迟线系统包括离散延迟部分，其中电感器以印刷螺旋形螺线管的形式实现，螺线管轴线在多层印刷电路板（PCB）的平面中。

公开(公告)号：US07968802B2

公开(公告)日：2011-06-28

申请号：US11967017

申请日：2007-12-29

Applicant: Yu-Chang Pai ,  Shou-Kuo Hsu ,  Chien-Hung Liu

Inventor： Yu-Chang Pai ,  Shou-Kuo Hsu ,  Chien-Hung Liu

IPC: H05K1/11 ,  H01P1/00

CPC classification number: H05K1/0245 ,  H05K1/0228 ,  H05K1/0251 ,  H05K1/115 ,  H05K2201/09636 ,  H05K2201/097

Abstract: A printed circuit board (PCB) includes a differential pair having a first differential trace and a second differential trace, a first via having an upper cap and a lower cap, and a second via having an upper cap and a lower cap. The first differential trace includes a first segment and a second segment, the second differential trace includes a third segment and a fourth segment. The first and the third segments are electrically coupled to the upper caps of the first and the second vias respectively. The second and the fourth segments are electrically coupled to the lower caps of the first and the second vias respectively. The first and the third segments extend from corresponding upper caps in different directions, the second and the fourth segments extend from corresponding lower caps in different directions.

Abstract translation: 印刷电路板（PCB）包括具有第一差分迹线和第二差分迹线的差分对，具有上盖和下盖的第一通孔以及具有上盖和下盖的第二通孔。 第一差分迹线包括第一段和第二段，第二差分迹线包括第三段和第四段。 第一和第三段分别电耦合到第一和第二通孔的上盖。 第二和第四段分别电耦合到第一和第二通孔的下盖。 第一和第三段从相应的上盖在不同的方向上延伸，第二和第四段从相应的下盖在不同的方向延伸。

公开(公告)号：US20110122589A1

公开(公告)日：2011-05-26

申请号：US12951099

申请日：2010-11-22

Applicant: LI-CHUN WU ,  YONG-CHUN XU ,  CHAO-TUNG HUANG ,  CHIH-MIN LIN ,  JIAN-SHE HU ,  KUO-CHUAN HUANG

Inventor： LI-CHUN WU ,  YONG-CHUN XU ,  CHAO-TUNG HUANG ,  CHIH-MIN LIN ,  JIAN-SHE HU ,  KUO-CHUAN HUANG

IPC: H05K1/18 ,  H05K3/30

CPC classification number: H05K1/165 ,  H01F27/28 ,  H01F27/2804 ,  H01R12/526 ,  H01R13/6633 ,  H05K1/181 ,  H05K2201/086 ,  H05K2201/097 ,  H05K2201/1003 ,  H05K2201/1034 ,  Y10T29/4913

Abstract: A magnetic element (100) includes a board unit (2) including a paddle board (21) having a row of first conductive vias (251) and a row of second conductive vias (252) for insertion of terminals (3), a number of embedded magnetic components (22), and a number of SMDs (surface mount devices) (23) mounted on the paddle board by SMT (surface mount technology). Each embedded magnetic component includes a magnetic core (221) embedded in the paddle board, and a number of PCB (printed circuit board) layout traces (222) disposed in the paddle board. Each PCB layout trace includes a first PCB layout trace (222a) encircling around the magnetic core and connecting with the first conductive via, and a second PCB layout trace (222b) encircling around the magnetic core and connecting with the SMD.

Abstract translation: 磁性元件（100）包括板单元（2），其包括具有一列第一导电通孔（251）和用于插入端子（3）的一排第二导电通孔（252）的桨板（21） 的嵌入式磁性部件（22）和通过SMT（表面贴装技术）安装在桨板上的多个SMD（表面安装装置）（23）。 每个嵌入式磁性部件包括嵌入在该桨板中的磁芯（221）和布置在该桨板中的多个PCB（印刷电路板）布局轨迹（222）。 每个PCB布局迹线包括环绕磁芯并与第一导电通孔连接的第一PCB布局迹线（222a）和环绕磁芯并与SMD连接的第二PCB布局迹线（222b）。

公开(公告)号：US20100300732A1

公开(公告)日：2010-12-02

申请号：US12511286

申请日：2009-07-29

Applicant: QI-JIE CHEN

Inventor： QI-JIE CHEN

IPC: H05K1/02

CPC classification number: H05K1/0216 ,  H05K2201/09245 ,  H05K2201/097

Abstract: A multi-layer printed circuit board includes a first trace layer and a second trace layer. The second trace layer and the first trace layer are located on parallel horizontal planes. A first group of traces is laid on the first trace layer. A second group of traces is laid on the second trace layer. The second group of traces and the first group of traces are positioned on up and down positions of the first trace layer and the second trace layer. The first group of traces and the second group of traces extend in different directions.

Abstract translation: 多层印刷电路板包括第一迹线层和第二迹线层。 第二迹线层和第一迹线层位于平行水平面上。 第一组迹线放置在第一个迹线层上。 第二组轨迹铺设在第二个轨迹层上。 第二组迹线和第一组迹线位于第一迹线层和第二迹线层的上下位置。 第一组轨迹和第二组轨迹沿不同方向延伸。

公开(公告)号：US07724117B2

公开(公告)日：2010-05-25

申请号：US12013170

申请日：2008-01-11

Applicant: William R. Goyette ,  Frank B. Winter ,  Eric C. Johnston ,  Hardik Patel

Inventor： William R. Goyette ,  Frank B. Winter ,  Eric C. Johnston ,  Hardik Patel

IPC: H01F5/00

CPC classification number: H05K1/165 ,  H01F17/0013 ,  H01F17/0033 ,  H03H7/0115 ,  H03H2001/0085 ,  H05K1/162 ,  H05K3/429 ,  H05K2201/09672 ,  H05K2201/097

Abstract: A multilayer passive circuit topology is disclosed. In one embodiment, a multilayer circuit is provided. The multilayer circuit comprises a multilayer inductor comprising a first set of parallel conductive traces formed on a first layer, a second set of parallel conductive traces formed on a second layer spaced apart from the first layer; and a plurality of vias that connect respective parallel conductive traces from the first and second layer to form inductor windings. The multilayer circuit further comprises a multilayer capacitor connected to an end of the inductor by a coupling via, the capacitor comprising a first conductive plate and a second conductive plate being spaced apart from one another and being formed on different layers.

Abstract translation: 公开了一种多层无源电路拓扑。 在一个实施例中，提供了多层电路。 多层电路包括多层电感器，其包括形成在第一层上的第一组平行导电迹线，形成在与第一层间隔开的第二层上的第二组平行导电迹线; 以及多个通孔，其将来自第一和第二层的相应的平行导电迹线连接以形成电感器绕组。 多层电路还包括通过耦合通孔连接到电感器的端部的多层电容器，该电容器包括彼此间隔开并形成在不同层上的第一导电板和第二导电板。