公开(公告)号：US07612501B2

公开(公告)日：2009-11-03

申请号：US11276035

申请日：2006-02-10

Applicant: Sung-Tae Kim

Inventor： Sung-Tae Kim

IPC: H01J17/49 ,  H01L31/0312 ,  G09G3/10

CPC classification number: H05K3/361 ,  H01J11/10 ,  H01J11/46 ,  H05K1/117 ,  H05K3/323 ,  H05K2201/09427 ,  H05K2201/098

Abstract: A plasma display apparatus comprising a connector is provided. The plasma display apparatus comprises a plasma display panel comprising an electrode of a predetermined width and a connector comprising an electrode line of a width narrower than the predetermined width of the electrode to supply a driving signal to the electrode. A distance between the electrode line and an adjacent electrode line is longer than a distance between the electrode and an adjacent electrode.

Abstract translation: 提供了包括连接器的等离子体显示装置。 等离子体显示装置包括等离子体显示面板，其包括预定宽度的电极和包括宽度比电极的预定宽度窄的电极线的连接器，以向电极提供驱动信号。 电极线和相邻电极线之间的距离比电极和相邻电极之间的距离长。

公开(公告)号：US20080218285A1

公开(公告)日：2008-09-11

申请号：US11715504

申请日：2007-03-08

Applicant: Shih-Kun Yeh

Inventor： Shih-Kun Yeh

IPC: H01P3/08

CPC classification number: H05K1/0237 ,  H01P3/081 ,  H05K1/0393 ,  H05K3/281 ,  H05K2201/0191 ,  H05K2201/09236 ,  H05K2201/09318 ,  H05K2201/098

Abstract: A high-speed digital transmission signal line providing better dynamic resistance to be applied in an LVDS transmission system and functioning as an electronic line, an optical line, and a serial advanced technology attachment (SATA) includes a conductive layer in thickness of 0.018˜0.1 mm and in width of 0.2˜0.8 mm; a first and a second insulation layers each in thickness of 0.04˜0.3 mm being respectively disposed on both sides of the conductive layer; and a ground plate.

Abstract translation: 在LVDS传输系统中提供更好的动态电阻并且用作电子线路，光线路和串行高级技术附件（SATA）的高速数字传输信号线包括厚度为0.018〜0.1的导电层 mm，宽度为0.2〜0.8 mm; 分别设置在导电层两侧的厚度为0.04〜0.3mm的第一和第二绝缘层; 和接地板。

公开(公告)号：US20080055291A1

公开(公告)日：2008-03-06

申请号：US11838415

申请日：2007-08-14

Applicant: In-Yong HWANG ,  Sun-Kyu SON

Inventor： In-Yong HWANG ,  Sun-Kyu SON

IPC: G06F3/038 ,  H01L23/48

CPC classification number: H05K3/361 ,  H01L24/83 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/83851 ,  H01L2924/01079 ,  H01L2924/01087 ,  H05K3/323 ,  H05K2201/098 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A chip film package which can achieve a fine pitch and a display panel assembly having the same are provided. The chip film package includes a base film made of an insulating material, a wire pattern formed on the base film to form a predetermined circuit, and a lead which is formed at one end of the wire pattern to be electrically connected to an external terminal, wherein a width (Wb) of the bottom surface of the lead adjacent to the base film is smaller than a width (Wt) of the top surface of the lead connected to the external terminal.

Abstract translation: 提供了能够实现精细间距的芯片薄膜封装以及具有该间距的显示面板组件。 芯片膜封装包括由绝缘材料制成的基膜，形成在基膜上以形成预定电路的引线图案，以及形成在引线图案的一端以与外部端子电连接的引线， 其中，与所述基底膜相邻的所述引线的底面的宽度（Wb）小于与所述外部端子连接的所述引线的顶面的宽度（Wt）。

公开(公告)号：US20070273047A1

公开(公告)日：2007-11-29

申请号：US11763861

申请日：2007-06-15

Applicant: Toru Nakai ,  Masanori Tamaki

Inventor： Toru Nakai ,  Masanori Tamaki

IPC: H01L23/52 ,  H01L23/48 ,  H01L29/40 ,  H01L21/44

CPC classification number: H05K1/0242 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2924/15311 ,  H05K1/0216 ,  H05K1/0245 ,  H05K3/28 ,  H05K3/4602 ,  H05K3/4644 ,  H05K2201/09236 ,  H05K2201/098

Abstract: A printed wiring board having an interlayer insulation layer and conductive circuits formed on the interlayer insulation layer. The conductive circuits include a first conductive circuit and a second conductive circuit positioned adjacent to each other, and the first and second conductive circuits satisfy a formula, 0.10 T≦|W1−W2|≦0.73 T, where W1 represents an upper conductive circuit space between the first and second conductive circuits, W2 represents a lower conductive circuit space between the first and second conductive circuits, and T represents a thickness of the first and second conductive circuits.

Abstract translation: 一种具有层间绝缘层和形成在层间绝缘层上的导电电路的印刷电路板。 导电电路包括彼此相邻定位的第一导电电路和第二导电电路，第一和第二导电电路满足公式0.10 T <= | W 1 -W 2 | <= 0.73 T，其中W 1表示 第一和第二导电电路之间的上部导电电路空间，W 2表示第一和第二导电电路之间的较低的导电电路空间，T表示第一和第二导电电路的厚度。

公开(公告)号：US07294532B2

公开(公告)日：2007-11-13

申请号：US11146610

申请日：2005-06-07

Applicant: Hiroyuki Imamura ,  Nobuyuki Koutani

Inventor： Hiroyuki Imamura ,  Nobuyuki Koutani

IPC: H01L21/44

CPC classification number: H01L21/4853 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/4985 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/83192 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/3025 ,  H05K1/111 ,  H05K3/243 ,  H05K2201/0367 ,  H05K2201/09727 ,  H05K2201/098 ,  H05K2201/0989 ,  H05K2201/10674 ,  Y02P70/611 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A method for manufacturing a semiconductor device that includes mounting a semiconductor chip on a circuit board having an insulating substrate, a plurality of wiring layers arranged on the insulating substrate, and bumps formed on the wiring layers respectively, in which the bump is provided across a longitudinal direction of a corresponding one of the wiring layers so as to extend over regions on both sides of the wiring layer and contact a surface of the insulating substrate, without a stepped portion formed on a surface of the bump, and a cross sectional shape of the bump taken in a width direction of the wiring layer is such that a central portion is higher than both side portions. The method also includes connecting electrode pads of the semiconductor chip to the bumps, thereby achieving connection between the electrode pads of the semiconductor chip and the wiring layers via the bumps.

Abstract translation: 一种半导体器件的制造方法，其包括将半导体芯片安装在具有绝缘基板的电路板上，布置在所述绝缘基板上的多个布线层以及分别形成在所述布线层上的凸块， 相对应的一个布线层的纵向方向延伸到布线层的两侧的区域上并与绝缘基板的表面接触，而不形成在凸起的表面上的阶梯部分，并且横截面形状 在布线层的宽度方向上取得的隆起部使得中央部高于两侧部。 该方法还包括将半导体芯片的电极焊盘连接到凸块，从而通过凸块实现半导体芯片的电极焊盘与布线层之间的连接。

公开(公告)号：US20070181994A1

公开(公告)日：2007-08-09

申请号：US10598524

申请日：2005-03-02

Applicant: Katsuya Fukase ,  Toyoaki Sakai ,  Munetoshi Irisawa ,  Toyokazu Komuro ,  Yasuo Kaneda ,  Masanori Natsuka ,  Wakana Aizawa

Inventor： Katsuya Fukase ,  Toyoaki Sakai ,  Munetoshi Irisawa ,  Toyokazu Komuro ,  Yasuo Kaneda ,  Masanori Natsuka ,  Wakana Aizawa

IPC: H01L23/12 ,  H01L21/00

CPC classification number: H05K3/064 ,  H05K1/116 ,  H05K3/0094 ,  H05K3/061 ,  H05K3/065 ,  H05K3/108 ,  H05K3/421 ,  H05K3/427 ,  H05K2201/09381 ,  H05K2201/09563 ,  H05K2201/09581 ,  H05K2201/098 ,  H05K2203/0517 ,  H05K2203/0577 ,  H05K2203/0582 ,  H05K2203/1184 ,  H05K2203/1394

Abstract: As means for solving a problem of a positional shift of a land and a hole which is caused by an alignment in the formation of an etching resist layer and a plated resist layer in a method of manufacturing a circuit board, there are provided a method of manufacturing a circuit board including the steps of forming a first resin layer on a surface of an insulating substrate having a conductive layer on the surface and an internal wall of a through hole or/and a non-through hole, forming a second resin layer which is insoluble or slightly soluble in a developing solution for the first resin layer on the first resin layer provided on the surface conductive layer, and removing the first resin layer provided over the hole with the developing solution for the first resin layer, and a method of manufacturing a circuit board including the step of uniformly charging a surface of the first resin layer to induce a potential difference to the first resin layer provided over the hole and the first resin layer provided on the surface conductive layer before forming the second resin layer. Moreover, there is provided a circuit board having a hole with a small positional shift and high precision.

Abstract translation: 作为在电路基板的制造方法中解决在形成抗蚀剂层和电镀抗蚀剂层时的取向引起的焊盘和孔的位置偏移的问题的方法，提供了一种方法， 制造电路板，包括以下步骤：在表面上具有导电层的绝缘基板的表面上形成第一树脂层和通孔或/或非通孔的内壁，形成第二树脂层，所述第二树脂层 在设置在表面导电层上的第一树脂层上的第一树脂层的显影液中不溶或微溶，用第一树脂层的显影液除去设在孔上的第一树脂层， 制造电路板，包括对第一树脂层的表面均匀充电以对设置在孔上的第一树脂层引起电位差的步骤， 在形成第二树脂层之前，在表面导电层上设置阴极层。 此外，提供一种电路板，其具有位置偏移小且精度高的孔。

公开(公告)号：US20070151748A1

公开(公告)日：2007-07-05

申请号：US10584906

申请日：2004-12-17

Applicant: Andreas Ziegler ,  Norman Door ,  Werner Hammon ,  Markus Luthi

Inventor： Andreas Ziegler ,  Norman Door ,  Werner Hammon ,  Markus Luthi

IPC: H01B7/08

CPC classification number: H05K3/245 ,  H01B7/0861 ,  H05K1/0393 ,  H05K3/12 ,  H05K3/207 ,  H05K3/281 ,  H05K3/4611 ,  H05K3/4635 ,  H05K2201/0179 ,  H05K2201/0715 ,  H05K2201/098 ,  H05K2203/0113 ,  H05K2203/1476

Abstract: A flexible carrier (10) having a base layer made of plastic and at least one conducting structure (20) which is impressed at least on the base layer (12) with an electrically conductive paint on one side thereof. The at least one electrically conducting layer (20) is arranged between the base layer (12), and at least one covering layer (14) made of plastic and each of the optionally other electrically conducting structures (22) are respectively arranged between two successive other covering layers. The base layer (12) is connected to the at least one covering layer (14) and each of the optionally other covering layers is connected to the adjacent covering layers.

Abstract translation: 具有由塑料制成的基底层和至少一个导电结构（20）的柔性载体（10），其至少在其一侧上用导电涂料施加在基底层（12）上。 所述至少一个导电层（20）布置在所述基底层（12）之间，并且至少一个由塑料制成的覆盖层（14）和每个所述任选的其它导电结构（22）分别布置在两个连续的 其他覆盖层。 基底层（12）连接到至少一个覆盖层（14），并且任意其他覆盖层中的每一个连接到相邻的覆盖层。

公开(公告)号：US20060261465A1

公开(公告)日：2006-11-23

申请号：US11459951

申请日：2006-07-26

Applicant: Yuan-Liang Li ,  Jiangqi He ,  Dong Zhong ,  David Figueroa

Inventor： Yuan-Liang Li ,  Jiangqi He ,  Dong Zhong ,  David Figueroa

IPC: H01L23/12

CPC classification number: H01P3/081 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/66 ,  H01L2223/6627 ,  H01L2924/0002 ,  H01L2924/1903 ,  H05K1/0242 ,  H05K1/0245 ,  H05K1/0265 ,  H05K3/4644 ,  H05K2201/0715 ,  H05K2201/09236 ,  H05K2201/09672 ,  H05K2201/0979 ,  H05K2201/098 ,  H05K2203/0733 ,  H01L2924/00

Abstract: Trace configurations for carrying high-speed digital differential signals provide for reduced conduction loss and improved signal integrity. In one embodiment, a circuit board has a first set of conductive traces disposed on non-conductive material, and a second set of conductive traces parallel to the first set and disposed within the conductive material. The second set is separated from the first set by non-conductive material. Corresponding traces of the first and second sets may be in a stacked configuration. In other embodiments, conductive material may be provided between corresponding traces of the first and second sets resulting in an “I-shaped” or “U-shaped” cross-section. In yet other embodiments, the trace configurations have “T-shaped” and “L-shaped” cross-sections.

Abstract translation: 用于承载高速数字差分信号的跟踪配置提供了降低的传导损耗和改善的信号完整性。 在一个实施例中，电路板具有设置在非导电材料上的第一组导电迹线和平行于第一组并设置在导电材料内的第二组导电迹线。 第二组与非导电材料与第一组分离。 第一组和第二组的相应迹线可以是堆叠配置。 在其他实施例中，导电材料可以设置在第一组和第二组的相应迹线之间，导致“I形”或“U形”横截面。 在其它实施例中，迹线构造具有“T形”和“L形”横截面。

公开(公告)号：US20060216484A1

公开(公告)日：2006-09-28

申请号：US11388705

申请日：2006-03-24

Applicant: Atsushi Saita ,  Toshikazu Imaoka ,  Tetsuro Sawai

Inventor： Atsushi Saita ,  Toshikazu Imaoka ,  Tetsuro Sawai

IPC: B32B3/00 ,  B32B18/00

CPC classification number: H05K1/024 ,  B32B15/08 ,  H05K1/0242 ,  H05K1/0298 ,  H05K3/4688 ,  H05K2201/0191 ,  H05K2201/035 ,  H05K2201/0715 ,  H05K2201/098 ,  Y10T428/24917 ,  Y10T428/24926

Abstract: A wiring board in which a line can be made narrower and/or a transmission loss can be reduced is developed. The wiring board includes a first conductor and a second conductor maintained at the same potential, a dielectric material layer provided between the first and second conductors, and a third conductor embedded in the dielectric material layer. In the wiring board, a thickness of the dielectric material layer in a first region located between the third conductor and the first conductor is larger than a thickness of the dielectric material layer in a second region located between the third conductor and the second conductor. Moreover, a cross-sectional shape of the third conductor is trapezoidal in which angles of respective ends of the third conductor on a side closer to the second conductor are obtuse.

Abstract translation: 开发了可以使线路变窄和/或可以减小传输损耗的布线板。 布线板包括保持在相同电位的第一导体和第二导体，设置在第一和第二导体之间的介电材料层和嵌入电介质材料层中的第三导体。 在布线板中，位于第三导体和第一导体之间的第一区域中的电介质材料层的厚度大于位于第三导体和第二导体之间的第二区域中的电介质材料层的厚度。 此外，第三导体的横截面形状是梯形的，其中第三导体在更靠近第二导体的一侧的各端的角度是钝的。

公开(公告)号：US20060181189A1

公开(公告)日：2006-08-17

申请号：US11276035

申请日：2006-02-10

Applicant: Sung-Tae KIM

Inventor： Sung-Tae KIM

IPC: H01J1/14

CPC classification number: H05K3/361 ,  H01J11/10 ,  H01J11/46 ,  H05K1/117 ,  H05K3/323 ,  H05K2201/09427 ,  H05K2201/098

Abstract: A plasma display apparatus comprising a connector is provided. The plasma display apparatus comprises a plasma display panel comprising an electrode of a predetermined width and a connector comprising an electrode line of a width narrower than the predetermined width of the electrode to supply a driving signal to the electrode. A distance between the electrode line and an adjacent electrode line is longer than a distance between the electrode and an adjacent electrode.