公开(公告)号：US09437582B2

公开(公告)日：2016-09-06

申请号：US14257795

申请日：2014-04-21

Applicant: Tessera, Inc.

Inventor： David Gibson ,  Andy Stavros

IPC: H01L25/10 ,  H05K1/11 ,  H01L23/498 ,  H01L23/00 ,  H05K1/14 ,  H05K3/34 ,  H01L25/065

CPC classification number: H01L25/10 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/4985 ,  H01L24/14 ,  H01L24/17 ,  H01L25/0655 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2225/0652 ,  H01L2225/06527 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2225/1023 ,  H01L2225/107 ,  H01L2924/1437 ,  H01L2924/15311 ,  H05K1/112 ,  H05K1/141 ,  H05K3/3436 ,  H05K2201/10378 ,  H05K2201/10515 ,  H01L2224/48091 ,  H01L2924/00014

Abstract: A microelectronic assembly includes units superposed on one another to form at least one stack having a vertical direction. Each unit includes one or more microelectronic devices and has top and bottom surfaces. Top unit terminals are exposed at the top surfaces and bottom unit terminals are exposed at the bottom surfaces. The top and bottom unit terminals are provided at a set of ordered column positions. Each top unit terminal of the set, except the top unit terminals at the highest ordered column position, is connected to a respective bottom unit terminal of the same unit at a next higher ordered column position. Each bottom unit terminal of the set, except the bottom unit terminals of the lowest unit in the stack, is connected to a respective upper unit terminal of the next lower unit in the stack at the same column position.

Abstract translation: 微电子组件包括彼此叠置以形成具有垂直方向的至少一个堆叠的单元。 每个单元包括一个或多个微电子器件，并且具有顶表面和底表面。 顶部单元端子在顶部表面露出，底部单元端子暴露在底部表面。 顶部和底部单元端子设置在一组有序列位置。 除了在最高有序列位置的顶部单元端子之外，组件的每个顶部单元端子在下一个更高排序的列位置处连接到同一单元的相应底部单元端子。 除了堆叠中最低单元的底部单元端子之外，组件的每个底部单元端子连接到堆叠中的下一个下部单元的相应上部单元端子处于相同的列位置。

公开(公告)号：US09431366B2

公开(公告)日：2016-08-30

申请号：US14705005

申请日：2015-05-06

Applicant: International Business Machines Corporation

Inventor： Mario J. Interrante ,  Katsuyuki Sakuma

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/498 ,  H01L21/48

CPC classification number: H05K3/3494 ,  H01L21/4853 ,  H01L21/50 ,  H01L21/563 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/562 ,  H01L24/17 ,  H01L24/75 ,  H01L24/81 ,  H01L2224/131 ,  H01L2224/16113 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/75252 ,  H01L2224/75272 ,  H01L2224/75283 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/15311 ,  H01L2924/2064 ,  H01L2924/20641 ,  H01L2924/20642 ,  H01L2924/20643 ,  H01L2924/20644 ,  H01L2924/20645 ,  H01L2924/3511 ,  H01L2924/3841 ,  H05K1/0271 ,  H05K1/181 ,  H05K2201/10378 ,  H05K2201/10734 ,  H05K2201/10977 ,  H05K2203/1316 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A method of forming a 3D package. The method may include joining an interposer to a laminate chip carrier with the solid state diffusion of a first plurality of solder bumps by applying a first selective non-uniform heat and first uniform pressure; joining a top chip to the interposer with the solid state diffusion of a second plurality of solder bumps by applying a second selective non-uniform heat and second uniform pressure; heating the 3D package, the first and second pluralities of solder bumps to a temperature greater than the reflow temperature of the first and second pluralities of solder bumps, where the second plurality of solder bumps achieves the reflow temperature before the first plurality of solder bumps, where the first and second selective non-uniform heats being less that the reflow temperature of the first and second pluralities of solder bumps, respectively.

Abstract translation: 一种形成3D封装的方法。 该方法可以包括通过施加第一选择性不均匀的热和第一均匀压力将插入件连接到具有第一多个焊料凸块的固态扩散的层压芯片载体; 通过施加第二选择性不均匀的热和第二均匀压力将第二多个焊料凸块的固态扩散连接到所述插入件的顶部芯片; 将所述第一和第二多个焊料凸起加热到大于所述第一和第二多个焊料凸块的回流温度的温度，其中所述第二多个焊料凸块在所述第一多个焊料凸点之前达到回流温度， 其中第一和第二选择性不均匀热分别小于第一和第二多个焊料凸块的回流温度。

公开(公告)号：US20160212849A1

公开(公告)日：2016-07-21

申请号：US14960638

申请日：2015-12-07

Applicant: FUJITSU LIMITED

Inventor： Taiki Uemura ,  KOZO SHIMIZU ,  Seiki Sakuyama

IPC: H05K1/18 ,  C22C28/00 ,  C22C13/00 ,  H05K3/34 ,  B23K35/26

CPC classification number: C22C28/00 ,  B23K35/26 ,  B23K35/262 ,  B23K35/3006 ,  B23K35/302 ,  B23K35/40 ,  C22C13/00 ,  H01L24/00 ,  H05K3/3436 ,  H05K3/3463 ,  H05K2201/10378 ,  H05K2201/10674

Abstract: An electronic apparatus includes: a first electronic component including a first electrode; solder on the first electrode; and a phase containing In, Ag, and Cu, the phase being dispersed and included in the solder.And a method for manufacturing an electronic apparatus, the method includes: forming solder on a first electrode of a first component, the solder including a phase containing In, Ag, and Cu, the phase being dispersed in the solder.

Abstract translation: 一种电子设备，包括：第一电子部件，包括第一电极; 焊接在第一电极上; 以及包含In，Ag和Cu的相，该相分散并包含在焊料中。 一种电子设备的制造方法，其特征在于，在第一部件的第一电极上形成焊料，所述焊料包含含有In，Ag，Cu的相，所述相分散在所述焊料中。

公开(公告)号：US20160192498A1

公开(公告)日：2016-06-30

申请号：US15062480

申请日：2016-03-07

Applicant: FUJITSU LIMITED

Inventor： Teru Nakanishi ,  Nobuyuki Hayashi ,  Masaru Morita ,  Yasuhiro YONEDA

IPC: H05K1/18

CPC classification number: H05K1/0296 ,  H01L23/13 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/4985 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05647 ,  H01L2224/1379 ,  H01L2224/13839 ,  H01L2224/13847 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2924/01004 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/15311 ,  H05K1/181 ,  H05K3/3436 ,  H05K2201/10287 ,  H05K2201/10378 ,  H05K2201/10424 ,  H05K2201/10719 ,  Y02P70/613 ,  H01L2924/00

Abstract: A semiconductor device includes: a wiring board including a first electrode pad on a surface thereof; a circuit board disposed to stand on the wiring board, and including an interconnection connected to the first electrode pad; and a semiconductor package disposed to face the wiring board with the circuit board interposed therebetween, and including a second electrode pad on a surface thereof, the second electrode pad being connected to the interconnection.

Abstract translation: 半导体器件包括：布线板，其表面上包括第一电极焊盘; 电路板，被布置成站立在所述布线板上，并且包括连接到所述第一电极焊盘的互连; 以及半导体封装，其设置成与所述布线板面对所述电路板，并且在其表面上包括第二电极焊盘，所述第二电极焊盘连接到所述互连。

公开(公告)号：US20160163626A1

公开(公告)日：2016-06-09

申请号：US14706101

申请日：2015-05-07

Applicant: PHOENIX PIONEER TECHNOLOGY CO., LTD.

Inventor： Pao-Hung Chou ,  Shih-Ping Hsu

IPC: H01L23/498 ,  H05K3/46 ,  H01L21/683 ,  H05K1/11 ,  H01L21/48 ,  H05K3/06 ,  H05K3/40

CPC classification number: H01L23/49822 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/6835 ,  H01L23/13 ,  H01L23/49827 ,  H01L2221/68345 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/73204 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/0284 ,  H05K1/0296 ,  H05K1/111 ,  H05K3/061 ,  H05K3/40 ,  H05K2201/10378 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: The invention provides an interposer substrate and a method of fabricating the same. The method includes: etching a carrier to form a recessed groove thereon; filling a dielectric material in the recessed groove to form a first dielectric material layer, or forming a patterned first dielectric material layer on the carrier; forming a first wiring layer, a first conductive block and a second dielectric material layer on the carrier and the first dielectric material layer sequentially, with the first wiring layer and the first conductive block embedded in the second dielectric material layer; and forming a second wiring layer and a second conductive block on the second dielectric material layer. A coreless interposer substrate having fine pitches is thus fabricated.

Abstract translation: 本发明提供一种插入式基板及其制造方法。 该方法包括：蚀刻载体以在其上形成凹槽; 在所述凹槽中填充介电材料以形成第一介电材料层，或在所述载体上形成图案化的第一介电材料层; 在载体和第一介电材料层上依次形成第一布线层，第一导电块和第二介电材料层，第一布线层和第一导电块嵌入第二介电材料层中; 以及在所述第二电介质材料层上形成第二布线层和第二导电块。 因此制造具有细间距的无芯内插器基板。

公开(公告)号：US20160143140A1

公开(公告)日：2016-05-19

申请号：US14860718

申请日：2015-09-22

Applicant: Mediatek Inc.

Inventor： Sheng-Ming Chang ,  Chia-Hui Liu ,  Shih-Chieh Lin ,  Chun-Ping Chen

IPC: H05K1/11 ,  H05K1/02

CPC classification number: H05K1/115 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/50 ,  H01L24/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/0262 ,  H05K1/0298 ,  H05K1/05 ,  H05K1/111 ,  H05K1/114 ,  H05K1/181 ,  H05K2201/09227 ,  H05K2201/095 ,  H05K2201/09509 ,  H05K2201/10378 ,  H05K2201/10674 ,  H05K2201/10734 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A printed circuit board includes a laminated core including at least an internal conductive layer, and a build-up layer on the laminated core. The build-up layer includes a top conductive layer. A plurality of microvias is disposed in the build-up layer to electrically connect the top conductive layer with the internal conductive layer. A power/ground ball pad array is disposed in the top conductive layer. The power/ground ball pad array includes power ball pads and ground ball pads arranged in an array with a fixed ball pad pitch P. The power/ground ball pad array includes a 4-ball pad unit area that is comprised of only one ground ball pad and three power ball pads, or comprised of only one power ball pad and three ground ball pads. The 4-ball pad unit area has a rectangular shape and a dimension of about 2P×2P.

Abstract translation: 印刷电路板包括至少包括内部导电层和层压芯上的堆积层的叠层芯。 堆积层包括顶部导电层。 多个微孔设置在积层层中以将顶部导电层与内部导电层电连接。 电源/接地球垫阵列设置在顶部导电层中。 电源/接地球垫阵列包括排列成具有固定球垫间距P的阵列的功率球垫和接地球垫。电源/接地球垫阵列包括仅由一个接地球组成的4球垫单元区域 垫和三个电源球垫，或仅由一个电源球垫和三个地球垫组成。 四球垫单位面积为矩形，尺寸约为2P×2P。

公开(公告)号：US20160141237A1

公开(公告)日：2016-05-19

申请号：US14541803

申请日：2014-11-14

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Mukta G. FAROOQ ,  William F. LANDERS ,  Jin LIU ,  Andrew J. MARTIN ,  Kathryn E. SCHLICHTING ,  Melissa A. SMITH

IPC: H01L23/498 ,  H05K3/00 ,  H05K3/42 ,  H01L21/48 ,  H05K1/03

CPC classification number: H01L23/49827 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/145 ,  H01L23/15 ,  H01L23/49822 ,  H01L23/49866 ,  H01L2924/0002 ,  H05K1/0306 ,  H05K1/0313 ,  H05K3/0017 ,  H05K3/007 ,  H05K3/423 ,  H05K2201/10378 ,  H05K2203/0733 ,  H05K2203/143 ,  H05K2203/1461 ,  H01L2924/00

Abstract: A three-dimensional organic structure or glass interposer structure and methods of manufacture are disclosed. The method includes forming lined metal vias in a substrate. The method further includes removing the substrate, leaving the lined metal vias. The method further includes forming a new substrate about the lined metal vias. The method also includes connecting the lined metal vias to wiring layers using back end of the line processes.

Abstract translation: 公开了三维有机结构或玻璃内插器结构及其制造方法。 该方法包括在衬底中形成衬里的金属通孔。 该方法还包括去除衬底，留下衬里的金属通孔。 该方法还包括围绕衬里的金属通孔形成新的衬底。 该方法还包括使用线路工艺的后端将衬里金属通孔连接到布线层。

公开(公告)号：US20160128206A9

公开(公告)日：2016-05-05

申请号：US13866835

申请日：2013-04-19

Applicant: Palo Alto Research Center Incorporated

Inventor： Eugene M. Chow

IPC: H05K3/32

CPC classification number: H05K3/32 ,  G01R1/06727 ,  H01L21/56 ,  H01L21/6835 ,  H01L23/3157 ,  H01L23/48 ,  H01L23/49811 ,  H01L24/13 ,  H01L24/16 ,  H01L24/72 ,  H01L24/73 ,  H01L2221/68331 ,  H01L2221/68377 ,  H01L2221/68381 ,  H01L2224/1161 ,  H01L2224/1182 ,  H01L2224/1191 ,  H01L2224/13008 ,  H01L2224/13012 ,  H01L2224/13016 ,  H01L2224/13022 ,  H01L2224/13026 ,  H01L2224/131 ,  H01L2224/1355 ,  H01L2224/13564 ,  H01L2224/136 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/81192 ,  H01L2224/81801 ,  H01L2224/819 ,  H01L2924/0001 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01042 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/01093 ,  H01L2924/014 ,  H01L2924/14 ,  H05K3/281 ,  H05K3/4007 ,  H05K3/4092 ,  H05K2201/10378 ,  Y10T29/49124 ,  Y10T29/49147 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/13099

Abstract: An interposer including stress-engineered nonplanar microsprings may provide interconnection of bonding pads of electronic structures disposed above and below the interposer. The lateral offset between an anchor portion of a microspring disposed for contact at a bottom surface of the interposer and the tip of the microspring located in a free portion of the microspring for contact and deflection over a top surface of the interposer permits the interconnection of devices having different bonding pad pitches. Microspring contacts at the free portion permit temporary interconnection of devices, while solder applied over the free portion permit permanent connection of devices to the interposer.

公开(公告)号：US20160111215A1

公开(公告)日：2016-04-21

申请号：US14671714

申请日：2015-03-27

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Sang Soo PARK ,  Soon Ju LEE ,  Young Ghyu AHN ,  Heung Kil PARK

IPC: H01G4/30 ,  H01G4/012 ,  H01G4/224 ,  H01C7/10 ,  H05K1/02 ,  H01L41/083 ,  H01C7/00 ,  H01G4/12 ,  H05K1/18

CPC classification number: H01G4/30 ,  H01C1/14 ,  H01C1/148 ,  H01C7/008 ,  H01C7/10 ,  H01C7/18 ,  H01G2/065 ,  H01G4/12 ,  H01G4/232 ,  H05K1/141 ,  H05K3/3442 ,  H05K2201/049 ,  H05K2201/10015 ,  H05K2201/10378 ,  H05K2201/2045 ,  Y02P70/613

Abstract: There is provided a chip electronic component may include: a ceramic body; external electrodes formed on both side portions of the ceramic body; and an interposer supporting the ceramic body and electrically connected to the external electrodes, wherein the interposer includes first and second terminal electrodes formed on both side portions thereof and recesses formed inwardly in the first and second terminal electrodes.

Abstract translation: 提供一种芯片电子部件可以包括：陶瓷体; 形成在陶瓷体的两侧部的外部电极; 以及支撑陶瓷体并与外部电极电连接的插入件，其中插入件包括形成在其两侧部分上的第一和第二端子电极以及在第一和第二端子电极内部形成的凹部。

公开(公告)号：US09318425B2

公开(公告)日：2016-04-19

申请号：US13212467

申请日：2011-08-18

Applicant: Teru Nakanishi ,  Nobuyuki Hayashi ,  Masaru Morita ,  Yasuhiro Yoneda

Inventor： Teru Nakanishi ,  Nobuyuki Hayashi ,  Masaru Morita ,  Yasuhiro Yoneda

IPC: H05K1/00 ,  H01L23/498 ,  H01L23/13 ,  H05K3/34 ,  H01L23/00

CPC classification number: H05K1/0296 ,  H01L23/13 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/4985 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05647 ,  H01L2224/1379 ,  H01L2224/13839 ,  H01L2224/13847 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2924/01004 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/15311 ,  H05K1/181 ,  H05K3/3436 ,  H05K2201/10287 ,  H05K2201/10378 ,  H05K2201/10424 ,  H05K2201/10719 ,  Y02P70/613 ,  H01L2924/00

Abstract: A semiconductor device includes: a wiring board including a first electrode pad on a surface thereof; a circuit board disposed to stand on the wiring board, and including an interconnection connected to the first electrode pad; and a semiconductor package disposed to face the wiring board with the circuit board interposed therebetween, and including a second electrode pad on a surface thereof, the second electrode pad being connected to the interconnection.

Abstract translation: 半导体器件包括：布线板，其表面上包括第一电极焊盘; 电路板，被布置成站立在所述布线板上，并且包括连接到所述第一电极焊盘的互连; 以及半导体封装，其设置成与所述布线板面对所述电路板，并且在其表面上包括第二电极焊盘，所述第二电极焊盘连接到所述互连。