公开(公告)号：US20070012773A1

公开(公告)日：2007-01-18

申请号：US11448516

申请日：2006-06-07

Applicant: Marlin Mickle ,  James Cain ,  Michael Lovell ,  Junfeng Mei

Inventor： Marlin Mickle ,  James Cain ,  Michael Lovell ,  Junfeng Mei

IPC: G06K7/00

CPC classification number: G06K19/07749 ,  G06K19/07745 ,  H01L23/49838 ,  H01L24/24 ,  H01L24/29 ,  H01L24/82 ,  H01L24/83 ,  H01L2224/16 ,  H01L2224/24051 ,  H01L2224/24226 ,  H01L2224/2919 ,  H01L2224/76155 ,  H01L2224/82102 ,  H01L2224/838 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01087 ,  H01L2924/0665 ,  H01L2924/0781 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/19041 ,  H05K1/095 ,  H05K3/32 ,  H05K2201/10477 ,  H05K2203/1469 ,  H01L2924/00 ,  H01L2224/0401

Abstract: Described are methods of making an electronic device including an electronic component, such as an IC chip, connected to conducting traces provided on a substrate by depositing an electrically conductive polymer deposited onto the substrate. The electronic component may be placed on the substrate before or after the electrically conductive polymer is deposited. Once deposited, the electrically conductive polymer is cured. The electrically conductive polymer may be deposited in a number of ways, such as using a mask having a desired pattern and applying the electrically conductive polymer to the mask, by screen printing the electrically conductive polymer or by printing the electrically conductive polymer using ink jet printing techniques.

Abstract translation: 描述了制造电子器件的方法，该电子器件包括通过沉积沉积在衬底上的导电聚合物连接到设置在衬底上的导电迹线的诸如IC芯片的电子部件。 电子部件可以在导电聚合物沉积之前或之后放置在基板上。 一旦沉积，导电聚合物被固化。 可以以多种方式沉积导电聚合物，例如使用具有所需图案的掩模，并通过丝网印刷导电聚合物或通过使用喷墨印刷印刷导电聚合物将导电聚合物施加到掩模 技术

公开(公告)号：US20070004089A1

公开(公告)日：2007-01-04

申请号：US11517366

申请日：2006-09-08

Applicant: Nobuaki Ebihara ,  Naoshi Suzuki

Inventor： Nobuaki Ebihara ,  Naoshi Suzuki

IPC: H01L21/58 ,  H01L21/60

CPC classification number: H05K1/141 ,  H01L25/105 ,  H01L2225/1029 ,  H01L2225/107 ,  H01L2924/0002 ,  H05K1/144 ,  H05K1/145 ,  H05K3/321 ,  H05K3/3421 ,  H05K2201/0397 ,  H05K2201/10477 ,  H05K2201/10515 ,  H05K2201/10689 ,  H05K2201/10969 ,  H01L2924/00

Abstract: To mount a TSOP on an interposer substrate, leads provided to the TSOP are joined to pads of the interposer substrate by a thermosetting conductive resin, and the TSOP exclusive of the leads is joined to ground layers formed in the interposer substrate by a thermosetting conductive resin. The interposer substrates with the TSOPs mounted thereon are stacked in eight layers in such a manner that the TSOPs face downward. Then, leads of the upper interposer substrate are joined to pads formed in the rear face of the lower interposer substrate by a thermosetting conductive resin, so that the interposer substrates adjacent in a vertical direction are connected.

Abstract translation: 为了将TSOP安装在插入物基板上，通过热固性导电树脂将提供给TSOP的引线接合到插入器基板的焊盘，并且引线之外的TSOP通过热固性导电树脂与形成在插入器基板中的接地层接合 。 将其上安装有TSOP的插入物基板以使得TSOP面向下的方式以8层层叠。 然后，通过热固性导电树脂将上部插入器基板的引线接合到形成在下部插入器基板的后表面中的焊盘，使得在垂直方向上相邻的插入器基板被连接。

公开(公告)号：US20060151861A1

公开(公告)日：2006-07-13

申请号：US11035918

申请日：2005-01-13

Applicant: Jonathan Noquil ,  Connie Tangpuz ,  Romel Manatad ,  Stephen Martin ,  Rajeev Joshi ,  Venkat Iyer

Inventor： Jonathan Noquil ,  Connie Tangpuz ,  Romel Manatad ,  Stephen Martin ,  Rajeev Joshi ,  Venkat Iyer

IPC: H01L23/495

CPC classification number: H01L23/36 ,  H01L23/488 ,  H01L2224/16 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H05K3/341 ,  H05K2201/09681 ,  H05K2201/10166 ,  H05K2201/10477 ,  H05K2201/10689 ,  H05K2201/10969 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2224/0401

Abstract: A semiconductor die package is disclosed. It may include a semiconductor die having a first surface and a second surface, and a leadframe structure. A molding material may be formed around at least a portion of the die and at least a portion of the leadframe structure. A solderable layer may be on the exterior surface of the molding material and the first surface of the semiconductor die.

Abstract translation: 公开了一种半导体管芯封装。 它可以包括具有第一表面和第二表面的半导体管芯和引线框架结构。 模制材料可以围绕模具的至少一部分和引线框架结构的至少一部分形成。 可焊层可以在模制材料的外表面和半导体管芯的第一表面上。

公开(公告)号：US07044620B2

公开(公告)日：2006-05-16

申请号：US10836479

申请日：2004-04-30

Applicant: Paul D. Van Duyn

Inventor： Paul D. Van Duyn

IPC: F21V29/00

CPC classification number: H05K1/182 ,  F21S41/141 ,  F21S41/192 ,  F21S41/30 ,  F21S41/32 ,  F21S43/14 ,  F21S43/15 ,  F21S43/195 ,  F21S43/30 ,  F21S43/31 ,  F21S45/47 ,  F21V19/001 ,  F21V29/75 ,  F21V29/763 ,  F21W2107/10 ,  F21Y2103/10 ,  F21Y2115/10 ,  H05K1/0203 ,  H05K2201/10106 ,  H05K2201/10477 ,  H05K2201/1056

Abstract: A lamp assembly and methods of assembling the lamp assembly are provided. The lamp assembly comprises a printed circuit board (PCB) having a face surface, a rear surface opposite the face surface, electrical traces on the rear surface, and an opening extending from the face surface to the rear surface, and a light emitting diode (LED) emitter having a dome portion, a body, and a plurality of electrical terminals connected to the body, wherein the body of the LED emitter is adjacent the rear surface, the dome portion of the LED emitter extends through the opening in the PCB to the face surface, and the electrical terminals are connected to the electrical traces on the rear surface.

Abstract translation: 提供了灯组件和组装灯组件的方法。 灯组件包括具有面表面的印刷电路板（PCB），与表面相对的后表面，后表面上的电迹线和从表面延伸到后表面的开口;以及发光二极管（ LED）发射器，其具有圆顶部分，主体和连接到主体的多个电端子，其中LED发射器的主体邻近后表面，LED发射器的圆顶部分延伸穿过PCB中的开口， 面表面和电端子连接到后表面上的电迹线。

公开(公告)号：US20050270757A1

公开(公告)日：2005-12-08

申请号：US11188149

申请日：2005-07-22

Applicant: Thomas Credelle ,  Glenn Gengel ,  Roger Stewart ,  William Joseph

Inventor： Thomas Credelle ,  Glenn Gengel ,  Roger Stewart ,  William Joseph

IPC: G06K19/07 ,  G06K19/077 ,  H01L29/06 ,  H05K1/11 ,  H05K1/14 ,  H05K1/18 ,  H05K3/22 ,  H05K3/32 ,  H05K7/02

CPC classification number: H01L24/96 ,  G06K19/07749 ,  G06K19/0775 ,  G06K19/07752 ,  G06K19/07779 ,  G06K19/07783 ,  H01L24/24 ,  H01L24/82 ,  H01L24/95 ,  H01L29/0657 ,  H01L2224/24137 ,  H01L2224/24227 ,  H01L2224/95085 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/10158 ,  H01L2924/12041 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15155 ,  H01L2924/15165 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01Q1/2208 ,  H01Q7/00 ,  H05K1/141 ,  H05K1/183 ,  H05K3/222 ,  H05K3/321 ,  H05K2201/10477 ,  Y10T29/49002 ,  Y10T29/49016 ,  Y10T29/49018 ,  Y10T29/49117 ,  Y10T29/4913 ,  Y10T29/49204 ,  H01L2924/00

Abstract: Methods and apparatuses for an electronic assembly. The electronic assembly has a first object created and separated from a host substrate. The first object has a first electrical circuitry therein. A carrier substrate is coupled to the first object wherein the first object is being recessed below a surface of the carrier substrate. The carrier substrate further includes a first carrier connection pad and a second carrier connection pad that interconnect with the first object using metal connectors. A receiving substrate, which is substantially planar, including a second electrical circuitry, a first receiving connection pad, and a second receiving connection pad that interconnect with the second electrical circuitry using the metal connectors. The carrier substrate is coupled to the receiving substrate using the connection pads mentioned.

Abstract translation: 电子组件的方法和装置。 电子组件具有从主体衬底产生并分离的第一对象。 第一个对象在其中具有第一电路。 载体基板耦合到第一物体，其中第一物体正在凹陷在载体基底的表面下方。 载体基板还包括第一载体连接焊盘和使用金属连接器与第一对象互连的第二载体连接焊盘。 接收基板，其基本上是平面的，包括第二电路，第一接收连接焊盘和与使用金属连接器与第二电路互连的第二接收连接焊盘。 使用所述连接焊盘将载体衬底耦合到接收衬底。

公开(公告)号：US20050213308A1

公开(公告)日：2005-09-29

申请号：US11085342

申请日：2005-03-21

Applicant: Takeshi Suzuki ,  Toshiyuki Ilmura ,  Kazushige Osumi ,  Shinichi Tsuyuki

Inventor： Takeshi Suzuki ,  Toshiyuki Ilmura ,  Kazushige Osumi ,  Shinichi Tsuyuki

IPC: H01L25/18 ,  H01L23/50 ,  H01L25/04 ,  H01L25/16 ,  H05K1/00 ,  H05K1/02 ,  H05K1/05 ,  H05K1/14 ,  H05K3/28 ,  H05K3/34 ,  H05K7/06

CPC classification number: H05K1/141 ,  H01L25/16 ,  H01L25/165 ,  H01L2224/48091 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/30107 ,  H05K1/0218 ,  H05K1/056 ,  H05K3/284 ,  H05K3/3405 ,  H05K3/3421 ,  H05K2201/09772 ,  H05K2201/09781 ,  H05K2201/1034 ,  H05K2201/10477 ,  H05K2201/10515 ,  H05K2201/10977 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A hybrid integrated circuit device of the present invention includes: a circuit board having a front surface subjected to an insulation process; a conductive pattern formed on the front surface of the circuit board; a circuit element placed at a desired position on the conductive pattern and electrically connected to the conductive pattern; and a plurality of leads fixed to the conductive pattern and led to the outside. End portions of the leads which are led to the outside extend approximately parallel to the circuit board in a plane different from that of the front surface of the circuit board.

Abstract translation: 本发明的混合集成电路器件包括：具有经过绝缘处理的正面的电路板; 形成在所述电路板的前表面上的导电图案; 电路元件放置在导电图案上的期望位置并电连接到导电图案; 以及多个引线固定到导电图案并被引导到外部。 引导到外部的引线的端部在与电路板的前表面的平面不同的平面中大致平行于电路板延伸。

公开(公告)号：US20050023659A1

公开(公告)日：2005-02-03

申请号：US10897098

申请日：2004-07-23

Applicant: Sang-Yeop Lee ,  Cheul-Joong Youn

Inventor： Sang-Yeop Lee ,  Cheul-Joong Youn

IPC: H01L23/12 ,  H01L21/60 ,  H01L23/31 ,  H01L25/00 ,  H01L25/065 ,  H01L25/07 ,  H01L25/10 ,  H01L25/18 ,  H05K1/02 ,  H05K1/14 ,  H05K3/34 ,  H01L23/02

CPC classification number: H01L23/3128 ,  H01L24/45 ,  H01L24/48 ,  H01L25/105 ,  H01L25/16 ,  H01L2224/32225 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1076 ,  H01L2924/00014 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/19041 ,  H05K1/023 ,  H05K1/141 ,  H05K3/3436 ,  H05K2201/09972 ,  H05K2201/10477 ,  H05K2201/10515 ,  H05K2201/10674 ,  H05K2201/2036 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: A semiconductor chip package may include functional and packaging parts, which may be separated into first and second areas respectively, and designated only for a specific type of semiconductor material. The first area may be designated only for functional material, while the second area may be designated only for packaging material. The first area may include a semiconductor chip and/or passive elements, while the second area may include packaging material for example, solder and/or contact pads.

Abstract translation: 半导体芯片封装可以包括功能和封装部件，其可分别分成第一和第二区域，并且仅被指定用于特定类型的半导体材料。 第一个区域可以仅用于功能材料，而第二个区域可以仅用于包装材料。 第一区域可以包括半导体芯片和/或无源元件，而第二区域可以包括例如焊料和/或接触焊盘的封装材料。

公开(公告)号：US20040203260A1

公开(公告)日：2004-10-14

申请号：US10487401

申请日：2004-02-20

Inventor： Christian Block ,  Christian Faistauer ,  Bernhard Reichel

IPC: H01R012/00

CPC classification number: H05K1/141 ,  H05K1/147 ,  H05K1/182 ,  H05K1/189 ,  H05K3/3436 ,  H05K3/3463 ,  H05K3/363 ,  H05K3/368 ,  H05K2201/09072 ,  H05K2201/10371 ,  H05K2201/10477

Abstract: The invention relates to a component arrangement in which an electric component (5) is lowered into an indentation (4) of a circuit board (1) and in which the electric component (5) is attached to an auxiliary circuit board (6), which is connected in turn to the circuit board (1). By lowering the electric component (5) in the indentation (4) of the circuit board (1), the component remainder (U) can be reduced advantageously.

Abstract translation: 本发明涉及电气部件（5）下降到电路板（1）的凹口（4）中并且其中电气部件（5）附接到辅助电路板（6）的部件布置， 其依次连接到电路板（1）。 通过降低电路板（1）的凹部（4）中的电气部件（5），可以有利地降低部件余量（U）。

公开(公告)号：US06787921B2

公开(公告)日：2004-09-07

申请号：US10291019

申请日：2002-11-08

Applicant: Chien-Ping Huang

Inventor： Chien-Ping Huang

IPC: H01L2348

CPC classification number: H01L21/4853 ,  H01L23/3128 ,  H01L23/49816 ,  H01L24/48 ,  H01L25/0657 ,  H01L2224/05599 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/181 ,  H05K3/3436 ,  H05K3/3463 ,  H05K2201/094 ,  H05K2201/10234 ,  H05K2201/10477 ,  H05K2201/10992 ,  H05K2201/2036 ,  H05K2203/041 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: A solder ball array type package structure is able to control collapse. The package includes a substrate, a carrier, a plurality of dies, a molding compound and a plurality of solder balls. The substrate has at least one active surface. Pads are located on the first surface of the substrate. The carrier has at least an active surface and a back surface opposite the active surface. A plurality of dies are located on the back surface and the active surface of the carrier. The dies arranged on the active surface are electrically connected to the carrier by flip chip technology. A molding compound encapsulates on the back surface of the carrier to cover the dies on the back surface of the carrier. Solder balls having a base material are provided on the active surface of the carrier in array. At least three solder balls coated with the base material having a high melting-temperature core are further provided in the periphery of the array. The carrier is arranged such that the active surface faces the first surface of the substrate to allow each solder ball correspond to the one of the pads, respectively.

公开(公告)号：US20040163841A1

公开(公告)日：2004-08-26

申请号：US10474332

申请日：2004-04-23

Inventor： Thierry Herve

IPC: H05K001/11

CPC classification number: H05K3/363 ,  A61B5/04085 ,  A61B2562/222 ,  H05K1/118 ,  H05K3/321 ,  H05K3/361 ,  H05K2201/053 ,  H05K2201/09472 ,  H05K2201/10477 ,  H05K2201/10666 ,  H05K2203/0455

Abstract: The invention concerns a method for connecting first contact studs (16) of a structure (1) bearing electrodes (4) for measuring or for stimulating a physiological activity with second studs (17) of at least a downstream circuit (2), each second stud (17) being traversed by an opening (15) perforating the downstream circuit. The method comprises the following steps: a) placing the downstream circuit on said structure, so that the opening (15) of a second stud (17) is located opposite a first stud (16); and b) depositing in the opening (15) of the second stud (17) a conductive material (18) providing the connection between the first and the second stud opposite.

Abstract translation: 本发明涉及一种用于连接承载电极（4）的结构（1）的第一接触柱（16）的方法，用于测量或用于刺激至少下游电路（2）的第二螺柱（17）的生理活动，每个第二接触柱 螺柱（17）被穿过下游回路的开口（15）穿过。 该方法包括以下步骤：a）将下游电路放置在所述结构上，使得第二螺柱（17）的开口（15）位于与第一螺柱（16）相对的位置。 以及b）在所述第二螺柱（17）的所述开口（15）中沉积导电材料（18），所述导电材料（18）提供所述第一和第二螺柱相对的连接。