公开(公告)号：US20120256315A1

公开(公告)日：2012-10-11

申请号：US13495687

申请日：2012-06-13

Applicant: Thorsten Meyer ,  Markus Brunnbauer ,  Jens Pohl

Inventor： Thorsten Meyer ,  Markus Brunnbauer ,  Jens Pohl

IPC: H01L23/498

CPC classification number: H01L21/565 ,  H01L21/561 ,  H01L21/568 ,  H01L24/19 ,  H01L24/82 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24146 ,  H01L2224/32145 ,  H01L2224/73267 ,  H01L2224/83101 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2225/06524 ,  H01L2225/06548 ,  H01L2225/06565 ,  H01L2225/06568 ,  H01L2225/06586 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19042 ,  H01L2924/19043 ,  H05K1/185 ,  H05K2201/09118 ,  H05K2201/10515 ,  H05K2201/10674 ,  H05K2203/016 ,  H05K2203/1316 ,  H05K2203/1469 ,  H01L2224/82 ,  H01L2924/00

Abstract: A method for fabricating a device, a semiconductor chip package, and a semiconductor chip assembly is disclosed. One embodiment includes applying at least one semiconductor chip on a first form element. At least one element is applied on a second form element. A material is applied on the at least one semiconductor chip and on the at least one element.

Abstract translation: 公开了一种制造器件，半导体芯片封装和半导体芯片组件的方法。 一个实施例包括在第一成形元件上施加至少一个半导体芯片。 至少一个元素被应用在第二个表单元素上。 在至少一个半导体芯片上和该至少一个元件上施加材料。

公开(公告)号：US20120224332A1

公开(公告)日：2012-09-06

申请号：US13039309

申请日：2011-03-02

Applicant: JaEun Yun ,  Jong Wook Ju

Inventor： JaEun Yun ,  Jong Wook Ju

IPC: H05K7/00 ,  H05K3/30 ,  H05K3/32

CPC classification number: H05K3/328 ,  H01L23/3121 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/48471 ,  H01L2224/48479 ,  H01L2224/48483 ,  H01L2224/48992 ,  H01L2224/73203 ,  H01L2224/73207 ,  H01L2224/73215 ,  H01L2224/81192 ,  H01L2224/83101 ,  H01L2224/83192 ,  H01L2224/85051 ,  H01L2224/85186 ,  H01L2224/85951 ,  H01L2224/85986 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06575 ,  H01L2924/00014 ,  H01L2924/181 ,  H05K2201/10515 ,  H05K2201/1053 ,  H05K2203/049 ,  Y10T29/4913 ,  Y10T29/49146 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012 ,  H01L2224/4554

Abstract: An integrated circuit packaging system and method of manufacture thereof includes: a substrate; a first module attached to the substrate; a conductive connection built on the first module and conductively connected thereto; an adhesive spacer on the first module with the conductive connection exposed; and a second module on the adhesive spacer in conductive contact with the conductive connection and partially supported thereby.

Abstract translation: 一种集成电路封装系统及其制造方法，包括：基板; 附接到所述基板的第一模块; 建立在第一模块上并与其导电连接的导电连接; 第一模块上的粘合间隔物，其具有暴露的导电连接; 以及与导电连接导电接触并由其部分支撑的粘合剂间隔物上的第二模块。

公开(公告)号：US08207015B2

公开(公告)日：2012-06-26

申请号：US12772142

申请日：2010-04-30

Applicant: Guo Qiang Shen ,  Jae Hak Yee ,  Denver Zhu

Inventor： Guo Qiang Shen ,  Jae Hak Yee ,  Denver Zhu

IPC: H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC classification number: H01L23/49555 ,  H01L24/16 ,  H01L24/29 ,  H01L24/48 ,  H01L25/105 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/45014 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/83101 ,  H01L2225/1029 ,  H01L2924/00014 ,  H01L2924/01077 ,  H01L2924/14 ,  H01L2924/181 ,  H05K3/3421 ,  H05K2201/10515 ,  H01L2924/0665 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A method of manufacture of an integrated circuit packaging system includes: applying a conductive material on a support structure; providing a bottom integrated circuit package having a bottom lead extended therefrom; attaching the bottom lead to the conductive material; stacking a top integrated circuit package over the bottom integrated circuit package, the top integrated circuit package having a top lead extending therefrom and the top lead over the bottom lead; attaching a conductive paste at an end portion of the top lead; and forming a stacking joint by flowing the conductive paste and the conductive material, the stacking joint below the top lead as well as below and above the bottom lead.

Abstract translation: 集成电路封装系统的制造方法包括：将导电材料施加到支撑结构上; 提供具有从其延伸的底部引线的底部集成电路封装; 将底部引线附接到导电材料; 在顶部集成电路封装上堆叠顶部集成电路封装，顶部集成电路封装具有从其延伸的顶部引线和顶部引线穿过底部引线; 在顶部引线的端部附着导电膏; 并且通过使导电膏和导电材料流动，堆叠接头在顶部引线下方以及底部引线下方和上方而形成堆叠接头。

公开(公告)号：US20120146209A1

公开(公告)日：2012-06-14

申请号：US13074467

申请日：2011-03-29

Applicant: Yu-Shan Hu ,  Dyi-Chung Hu ,  Tzyy-Jang Tseng

Inventor： Yu-Shan Hu ,  Dyi-Chung Hu ,  Tzyy-Jang Tseng

IPC: H01L23/48 ,  H05K1/18 ,  H01L21/50

CPC classification number: H01L23/49827 ,  H01L23/3121 ,  H01L23/36 ,  H01L23/49816 ,  H01L23/49833 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0655 ,  H01L2223/6677 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/1412 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/16265 ,  H01L2224/16267 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/19011 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/351 ,  H05K3/3436 ,  H05K2201/10515 ,  H01L2924/00

Abstract: A packaging substrate having a through-holed interposer embedded therein is provided, which includes: a molding layer having opposite first and second surfaces; a through-holed interposer embedded in the molding layer and flush with the second surface; a redistribution-layer structure embedded in the molding layer and disposed on the through-holed interposer and having a plurality of electrode pads exposed from the first surface of the molding layer; and a built-up structure disposed on the second surface of the molding layer and electrically connected to the through-holed interposer. By embedding the through-holed interposer in the molding layer and forming the built-up structure on the second surface of the molding layer, the present invention eliminates the need of a core board and reduces the thickness of the overall structure. Further, since the through-holed interposer has a CIE close to or the same as that of a silicon wafer, the structural reliability during thermal cycle testing is improved.

Abstract translation: 提供一种具有嵌入其中的通孔插入器的封装基板，其包括：具有相对的第一和第二表面的成型层; 嵌入在模制层中并与第二表面齐平的穿孔插入器; 重分布层结构，其嵌入在所述成型层中并且设置在所述穿孔插入件上，并且具有从所述成型层的第一表面露出的多个电极焊盘; 以及设置在模制层的第二表面上并与穿孔插入件电连接的组合结构。 通过将贯穿孔插入件嵌入成型层中并在成型层的第二表面上形成积层结构，本发明消除了对于芯板的需要并减小了整体结构的厚度。 此外，由于通孔插入器的CIE与硅晶片的CIE接近或相同，所以热循环测试期间的结构可靠性得到改善。

公开(公告)号：US20120135569A1

公开(公告)日：2012-05-31

申请号：US13305564

申请日：2011-11-28

Applicant: David J. Corisis

Inventor： David J. Corisis

IPC: H01L21/56

CPC classification number: H01L25/0657 ,  H01L25/105 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/4911 ,  H01L2225/06582 ,  H01L2225/1023 ,  H01L2225/107 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H05K1/181 ,  H05K2201/10515 ,  H05K2201/10674 ,  H05K2201/10689 ,  H05K2201/10734 ,  Y02P70/611 ,  H01L2924/00014

Abstract: An assembly of microelectronic devices and method for forming an assembly of microelectronic devices. In one embodiment, the method includes positioning a first packaged microelectronic device adjacent to a support member having support member circuitry, with the first packaged microelectronic device having a first microelectronic die at least partially encased in a first encapsulant to define a first package configuration. The method can further include electrically connecting the first packaged microelectronic device to a first portion of the support member circuitry and positioning at least proximate to the first packaged microelectronic device a second packaged microelectronic device having a second microelectronic die at least partially encased in a second encapsulant to define a second package configuration different than the first package configuration. The first packaged microelectronic device can be positioned between the support member and the second packaged microelectronic device. The second packaged device can be coupled directly to a second portion of the support member circuitry. Accordingly, the second packaged microelectronic device can be connected directly to the support member without connecting the second packaged device to the first packaged device.

Abstract translation: 微电子器件的组件和用于形成微电子器件的组件的方法。 在一个实施例中，该方法包括将第一封装微电子器件定位成与具有支撑构件电路的支撑构件相邻，其中第一封装微电子器件具有至少部分地封装在第一密封剂中以限定第一封装构造的第一微电子管芯。 该方法还可以包括将第一封装微电子器件电连接到支撑构件电路的第一部分，并至少邻近第一封装微电子器件定位第二封装微电子器件，其具有至少部分地封装在第二密封剂中的第二微电子管芯 以定义与第一包配置不同的第二包配置。 第一封装的微电子器件可以位于支撑构件和第二封装的微电子器件之间。 第二封装装置可以直接耦合到支撑构件电路的第二部分。 因此，第二封装微电子器件可以直接连接到支撑构件而不将第二封装器件连接到第一封装器件。

公开(公告)号：US20120056235A1

公开(公告)日：2012-03-08

申请号：US13318504

申请日：2010-04-28

Applicant: Georg Bogner ,  Stefan Gruber

Inventor： Georg Bogner ,  Stefan Gruber

IPC: H01L33/62 ,  H01L33/48

CPC classification number: H05K1/183 ,  H01L25/167 ,  H01L2224/48091 ,  H01L2224/48227 ,  H05K1/181 ,  H05K2201/10106 ,  H05K2201/10515 ,  H05K2201/10674 ,  H05K2201/10977 ,  H05K2203/049 ,  Y02P70/611 ,  H01L2924/00014

Abstract: An optoelectronic module includes a radiation-emitting semiconductor component, an electrical component and a carrier substrate. The carrier substrate includes a top and a bottom, wherein first electrical connections are arranged on the bottom and second electrical connections are arranged on the top. The electrical component is arranged on the top of the carrier substrate and is electrically conductively connected with the first electrical connections. The radiation-emitting semiconductor component is arranged on the side of the electrical component remote from the carrier substrate. The radiation-emitting semiconductor component furthermore includes conductive structures electrically conductively connected with the second electrical connections.

Abstract translation: 光电子模块包括辐射发射半导体部件，电子部件和载体基板。 载体基板包括顶部和底部，其中第一电连接布置在底部上，而第二电连接布置在顶部。 电气部件布置在载体基板的顶部上并与第一电连接导电连接。 辐射发射半导体部件布置在远离载体基板的电子部件侧。 辐射发射半导体部件还包括与第二电连接导电连接的导电结构。

公开(公告)号：US08124450B2

公开(公告)日：2012-02-28

申请号：US12844795

申请日：2010-07-27

Applicant: Phan Hoang ,  Chinh Nguyen ,  Anthony Tran ,  Tung Dang

Inventor： Phan Hoang ,  Chinh Nguyen ,  Anthony Tran ,  Tung Dang

IPC: H01L21/00

CPC classification number: H01L23/3107 ,  H01L23/13 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49838 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2225/06572 ,  H01L2225/107 ,  H01L2225/1094 ,  H01L2924/01019 ,  H01L2924/01087 ,  H01L2924/09701 ,  H01L2924/15153 ,  H01L2924/15159 ,  H05K1/141 ,  H05K1/144 ,  H05K1/182 ,  H05K3/3436 ,  H05K2201/049 ,  H05K2201/09036 ,  H05K2201/10515 ,  H05K2201/10674

Abstract: An embodiment of the present invention is a technique to stack multiple devices using an interconnecting element. A board has a periphery and top and bottom surfaces. The top surface has top contact pads to attach to a first device. The bottom surface is milled down to form a cavity confined by vertical walls around the periphery. The cavity fits a second device. Bottom contact pads are formed on bottom side of the vertical walls. The bottom contact pads are raised with respect to the bottom side of the vertical walls. Traces internal to the board connect the bottom contact pads to the top contact pads.

Abstract translation: 本发明的实施例是使用互连元件堆叠多个设备的技术。 电路板具有外围和顶部和底部表面。 顶表面具有附接到第一装置的顶部接触垫。 底面被铣削以形成围绕周边的垂直壁限定的空腔。 该腔适合第二个装置。 底部接触垫形成在垂直壁的底侧。 底部接触垫相对于垂直壁的底侧升高。 电路板内部的跟踪将底部接触焊盘连接到顶部接触焊盘。

公开(公告)号：US08120927B2

公开(公告)日：2012-02-21

申请号：US12098474

申请日：2008-04-07

Applicant: Nan-Jang Chen ,  Hong-Chin Lin

Inventor： Nan-Jang Chen ,  Hong-Chin Lin

IPC: H05K1/11 ,  H05K1/14

CPC classification number: H05K1/0216 ,  H01L2924/0002 ,  H05K3/222 ,  H05K2201/0715 ,  H05K2201/093 ,  H05K2201/09336 ,  H05K2201/10363 ,  H05K2201/10515 ,  H05K2201/10689 ,  H01L2924/00

Abstract: A printed circuit board is disclosed. The printed circuit board comprises a substrate having a top surface and a bottom surface. A ground plane is on the bottom surface. A signal trace is on the top surface along a first direction. At least two isolated power planes are on the top surface adjacent to opposite sides of the signal trace, respectively. A conductive connection along a second direction couples to the two power planes, across the signal trace without electrically connecting to the signal trace, wherein the signal trace doesn't pass over any split of the ground plane.

Abstract translation: 公开了印刷电路板。 印刷电路板包括具有顶表面和底表面的基底。 地平面位于底面。 信号迹线沿着第一方向在顶表面上。 至少两个隔离的电源平面分别位于与信号迹线的相对侧相邻的顶表面上。 沿着第二方向的导电连接在信号迹线上耦合到两个电源层，而不与电信号迹线电连接，其中信号迹线不经过接地层的任何分裂。

公开(公告)号：US20110294315A1

公开(公告)日：2011-12-01

申请号：US13147939

申请日：2009-11-17

Applicant: Masahito Kawabata ,  Seiji Yamaguchi

Inventor： Masahito Kawabata ,  Seiji Yamaguchi

IPC: H01R12/71

CPC classification number: H05K1/141 ,  G06K7/0078 ,  H05K3/3442 ,  H05K3/403 ,  H05K2201/049 ,  H05K2201/09036 ,  H05K2201/10189 ,  H05K2201/10378 ,  H05K2201/10515 ,  H05K2201/2018 ,  H05K2201/2036

Abstract: Provided are a circuit board module and an electronic device provided with the same capable of increasing the strength of a card connector, with the configuration that the card connector is mounted to have a specific space from the board. The circuit board module is provided with a card connector portion 40 which includes a card insertion port from which a card C1 having at least one contact is inserted, and a housing chamber 42 which is formed to be communicated with the card insertion port to contain the card C1 therein; and a circuit board 10 having a surface which supports the card connector portion 40. The card connector portion 40 is provided with a spring contact portion which projects from a floor surface of the card connector which forms the housing chamber 42 at a side of the circuit board 10 into the housing chamber 42, and contacts the contact of the card C1 to secure the electrical connection with the contact, and at least one column member 31A is provided in a mount space S formed between the surface of the circuit board 10 and the card connector portion 40 so that the column member at least partly overlaps a beginning area which corresponds to a root portion of the spring contact portion which projects into the housing chamber 42.

Abstract translation: 提供了一种电路板模块和具有该电路板模块的电子设备，其能够增加卡连接器的强度，其中卡连接器被安装为具有与板的特定空间的配置。 电路板模块设置有卡连接器部分40，其包括插入有至少一个触点的卡C1的卡插入口和形成为与卡插入口连通以容纳该卡插入口的卡插入口 卡C1; 以及具有支撑卡连接器部分40的表面的电路板10.卡连接器部分40设置有弹簧接触部分，该弹簧接触部分从电路侧的形成容纳室42的卡连接器的地板表面突出 板10进入容纳室42中，并与卡C1的触点接触以固定与触点的电连接，并且至少一个柱构件31A设置在形成在电路板10的表面和 卡连接器部分40，使得柱构件至少部分地与对应于突出到壳体室42中的弹簧接触部分的根部分的起始区域重叠。

公开(公告)号：US20110249414A1

公开(公告)日：2011-10-13

申请号：US13139740

申请日：2008-12-15

Applicant: Robert E Krancher ,  Scott P. Saunders ,  Brian D. Ryder

Inventor： Robert E Krancher ,  Scott P. Saunders ,  Brian D. Ryder

IPC: H05K5/00 ,  H05K1/16 ,  H05K1/18

CPC classification number: H05K1/183 ,  H05K1/023 ,  H05K1/0298 ,  H05K2201/10515 ,  H05K2201/10636 ,  H05K2201/10689 ,  Y02P70/611

Abstract: A system for placing electronic devices in restricted spaces of a printed circuit board. At least some of the illustrative embodiments are systems comprising a printed circuit board that comprises at least one conductive layer and at least one insulative layer (an outer surface of the printed circuit board defines a first plane), a void within the printed circuit board (the void defines an aperture through the outer surface, the void has at least one side wall at least partially defined by the insulative layer, and the void has a bottom that defines a second plane substantially parallel to the first plane), a first electronic device coupled to the printed circuit board within the void, and a second electronic device coupled to the outer surface, the second electronic device at least partially occludes the aperture.

Abstract translation: 一种用于将电子设备放置在印刷电路板的有限空间中的系统。 至少一些示例性实施例是包括印刷电路板的系统，其包括至少一个导电层和至少一个绝缘层（印刷电路板的外表面限定第一平面），印刷电路板内的空隙 所述空隙限定穿过所述外表面的孔，所述空隙具有至少部分由所述绝缘层限定的侧壁，并且所述空隙具有限定基本平行于所述第一平面的第二平面的底部），第一电子装置 耦合到空隙内的印刷电路板，以及耦合到外表面的第二电子器件，第二电子器件至少部分地封闭孔。