公开(公告)号：US5500278A

公开(公告)日：1996-03-19

申请号：US188322

申请日：1994-01-28

Applicant: Takashi Nagasaka

Inventor： Takashi Nagasaka

IPC: H01L21/48 ,  H01L23/50 ,  H01L23/538 ,  H05K1/02 ,  H05K1/09 ,  H05K3/00 ,  H05K3/10 ,  H05K3/12 ,  H05K3/46 ,  B32B9/00

CPC classification number: H05K1/0265 ,  H01L21/4857 ,  H01L23/50 ,  H01L23/5383 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/19107 ,  H05K1/092 ,  H05K2201/0376 ,  H05K3/0044 ,  H05K3/005 ,  H05K3/107 ,  H05K3/1258 ,  H05K3/4611 ,  Y10S428/901 ,  Y10T428/24926

Abstract: This invention provides a multilayer substrate suited for hybrid ICs.The multilayer substrate is formed from a plurality of layered insulating layers, at least one of which is provided with an inner-layer wiring space extending in the planer direction of the insulating layers and filled with a conductive wiring material. The inner-layer wiring space, which can be in the form of a strip, is connected via through holes to flip chip ICs, resistors, etc., so as to form a circuit.The inner-layer wiring composed of a wiring space extending in the planer direction and filled with a conductive wiring material has a larger cross-sectional area for the passage of electric current and is lower in electrical resistivity, in comparison with conventional wiring formed by printing.

Abstract translation: 本发明提供了适用于混合IC的多层衬底。 多层基板由多层分层绝缘层形成，其中至少一层具有沿绝缘层的平面方向延伸并填充有导电布线材料的内层布线空间。 可以是带状形式的内层布线空间经由通孔连接到倒装芯片IC，电阻器等，以形成电路。 由沿平面方向延伸并填充有导电布线材料的布线空间构成的内层布线与通过印刷形成的常规布线相比具有较大的电流通过的横截面积并且电阻率较低 。

公开(公告)号：US5369881A

公开(公告)日：1994-12-06

申请号：US124268

申请日：1993-09-20

Applicant: Masaichi Inaba ,  Norimasa Fujita

Inventor： Masaichi Inaba ,  Norimasa Fujita

IPC: H05K3/02 ,  H05K3/00 ,  H05K3/04 ,  H05K3/06 ,  H05K3/10 ,  H05K3/20 ,  H05K3/22 ,  H05K3/24 ,  H05K3/28 ,  H05K3/38

CPC classification number: H05K3/045 ,  H05K3/108 ,  H05K3/205 ,  H05K3/28 ,  H05K2201/0347 ,  H05K2201/0376 ,  H05K2201/09036 ,  H05K2201/09881 ,  H05K2203/0152 ,  H05K2203/025 ,  H05K2203/0376 ,  H05K2203/0554 ,  H05K2203/0726 ,  H05K3/0023 ,  H05K3/0032 ,  H05K3/064 ,  H05K3/107 ,  H05K3/388 ,  Y10T29/49155

Abstract: This invention provides a method of forming a circuit wiring pattern which cannot be formed by a prior art method such as etching or plating. This method comprises a step of forming trenches for forming a circuit wiring pattern at predetermined positions on at least one of the surface of an insulating base material and then filling a conductive material into the trenches, a step of removing conductor layers in such a manner that the conductor layers formed by the step described above exist only in the trenches formed in the insulating base material and gap portions of the circuit wiring pattern comprising the conductor layers formed in the trenches of the insulating base material are exposed, and a step of forming an insulating surface protection layer.

Abstract translation: 本发明提供一种形成电路布线图案的方法，该方法不能用诸如蚀刻或电镀的现有技术方法形成。 该方法包括以下步骤：在绝缘基材的至少一个表面上的预定位置处形成用于形成电路布线图案的沟槽，然后将导电材料填充到沟槽中，以如下方式除去导体层的步骤： 由上述步骤形成的导体层仅存在于形成在绝缘基材中的沟槽中，并且包含形成在绝缘基材的沟槽中的导体层的电路布线图案的间隙部分露出， 绝缘表面保护层。

公开(公告)号：US5244538A

公开(公告)日：1993-09-14

申请号：US736357

申请日：1991-07-26

Applicant: Nalin Kumar

Inventor： Nalin Kumar

IPC: H01L21/48 ,  H05K3/00 ,  H05K3/04 ,  H05K3/10 ,  H05K3/14 ,  H05K3/18 ,  H05K3/38 ,  H05K3/46

CPC classification number: H01L21/4857 ,  H05K3/045 ,  H05K3/184 ,  H05K3/465 ,  H01J2201/30457 ,  H05K2201/0154 ,  H05K2201/0166 ,  H05K2201/0376 ,  H05K2201/2081 ,  H05K2203/0554 ,  H05K2203/107 ,  H05K2203/121 ,  H05K2203/1338 ,  H05K3/0023 ,  H05K3/0041 ,  H05K3/107 ,  H05K3/143 ,  H05K3/146 ,  H05K3/185 ,  H05K3/388 ,  H05K3/4661

Abstract: A method of patterning metal on a substrate without photolithography. The steps include providing a dielectric substrate, forming a metal mask in a predetermined pattern on the substrate without using a mask by direct-write deposition using a particle beam such as a liquid metal cluster force to form the mask, dry etching the substrate to form a plurality of channels therein, depositing a conductive metal into the channels, and removing the mask. The top of the substrate can then be planarized by polishing, or alternatively the dielectric between the metal lines can be etched. The invention is well suited for fabricating copper/polyimide substrates.

Abstract translation: 在没有光刻的基板上图案化金属的方法。 所述步骤包括提供电介质基板，在基板上以预定图案形成金属掩模，而不用使用诸如液体金属簇力的粒子束的直接写入沉积来形成掩模，干燥蚀刻基板以形成 多个通道，将导电金属沉积到通道中，以及去除掩模。 然后可以通过抛光将衬底的顶部平坦化，或者可以蚀刻金属线之间的电介质。 本发明非常适用于制造铜/聚酰亚胺基片。

公开(公告)号：US4912844A

公开(公告)日：1990-04-03

申请号：US230460

申请日：1988-08-10

Applicant: Frederick Parker

Inventor： Frederick Parker

IPC: H05K1/02 ,  H05K1/05 ,  H05K1/09 ,  H05K1/18 ,  H05K3/00 ,  H05K3/04 ,  H05K3/10 ,  H05K3/24 ,  H05K3/34

CPC classification number: H05K3/107 ,  H05K3/0014 ,  H05K3/041 ,  H05K3/045 ,  H05K3/3457 ,  H05K1/0203 ,  H05K1/021 ,  H05K1/056 ,  H05K1/09 ,  H05K1/183 ,  H05K2201/0129 ,  H05K2201/0305 ,  H05K2201/0355 ,  H05K2201/0376 ,  H05K2201/0382 ,  H05K2201/09036 ,  H05K2203/0108 ,  H05K2203/025 ,  H05K2203/1105 ,  H05K2203/1469 ,  H05K3/0061 ,  H05K3/244 ,  H05K3/3468 ,  Y10T29/49139 ,  Y10T29/49158

Abstract: A punch has a planar surface and raised portions extending from the planar surface. First ones of the raised portions may have a height of approximately 3-25 mils. Second ones of the raised portions may have a greater depth than the first raised portions. The punch may be heated and/applied to the planar surface of a substrate which may also be pre-heated and which has properties of becoming deformed when subjected to heat and pressure. The punch produces cavities and grooves in the substrate at the positions of the raised portions. Electrical components may be disposed in the cavities in the substrate and an electrically conductive material may be disposed in the grooves to communicate with the electrical components. The raised portions in the punch may be provided by printed circuit techniques or by matching or by laser techniques. Alternatively, a foil may be disposed on the planar surface of the punch and the raised portions of the punch. When the punch is applied to the substrate, the grooves and cavities are formed and the foil is transferred to the substrate on the planar surface and in the grooves and cavities in the substrate. The portions of the foil on the planar surface of the substrate may then be removed as by printed circuit techniques or machining or laser techniques so that only the portions of the foil in the grooves and the cavities remain. If desired, these portions of the foil may be electrically plated.

Abstract translation: 冲头具有从平面表面延伸的平坦表面和凸起部分。 凸起部分中的第一个可以具有大约3-25密耳的高度。 第二凸起部分可以具有比第一凸起部分更深的深度。 冲头可以被加热和/施加到也可以被预热的基底的平坦表面上，并且当经受热和压力时具有变形的性质。 冲头在凸起部分的位置处在基板中产生空腔和凹槽。 电气部件可以设置在基板的空腔中，并且导电材料可以设置在凹槽中以与电气部件连通。 冲头中的凸起部分可以通过印刷电路技术或通过匹配或通过激光技术来提供。 或者，箔可以设置在冲头的平面表面和冲头的凸起部分上。 当冲头施加到基板上时，形成凹槽和空腔，并且箔片被转移到基板上的平面表面和基板中的凹槽和空腔中。 然后可以通过印刷电路技术或机械加工或激光技术去除衬底的平面表面上的箔的部分，使得只有凹槽和空腔中的箔的部分保留。 如果需要，箔的这些部分可以被电镀。

公开(公告)号：US4912288A

公开(公告)日：1990-03-27

申请号：US71267

申请日：1987-07-01

Applicant: Anthony Atkinson ,  Richard Gray ,  Oscar L. Denes

Inventor： Anthony Atkinson ,  Richard Gray ,  Oscar L. Denes

IPC: B29C45/14 ,  B29C70/78 ,  H01B13/00 ,  H01C17/06 ,  H05K1/00 ,  H05K1/02 ,  H05K1/09 ,  H05K1/16 ,  H05K3/00 ,  H05K3/20

CPC classification number: B29C45/1418 ,  B29C45/0053 ,  B29C45/0055 ,  B29C70/78 ,  H05K3/0014 ,  H05K3/207 ,  B29C2045/14237 ,  B29C2791/006 ,  B29C45/14639 ,  B29C45/14778 ,  B29C45/14827 ,  B29C51/082 ,  B29C51/10 ,  B29C51/14 ,  B29K2067/00 ,  B29K2995/0005 ,  B29L2009/008 ,  B29L2031/3425 ,  H05K1/0284 ,  H05K1/095 ,  H05K1/165 ,  H05K2201/0376 ,  H05K2201/09018 ,  H05K2201/09118 ,  H05K2201/0999 ,  H05K2201/2009 ,  H05K2203/0156 ,  H05K2203/1327 ,  H05K3/007 ,  Y10T29/4916

Abstract: A method of providing an electrical circuit wherein a carrier, which is a film of insulating plastic material with a circuit pattern thereon is supported in a mould and a moulding material is applied by the application of heat and pressure to provide a substrate so that the circuit is embedded in or within a three-dimensional surface of the moulded substrate.

Abstract translation: PCT No.PCT / GB86 / 00523 Sec。 371日期1987年7月1日 102（e）日期1987年7月1日PCT提交1986年9月3日PCT公布。 第WO87 / 01557号公报 日期：1987年3月12日。一种提供电路的方法，其中将作为其上具有电路图案的绝缘塑料材料的膜的载体支撑在模具中，并且通过施加热和压力施加模制材料 提供基板，使得电路嵌入在模制基板的三维表面中或内。

公开(公告)号：US4853277A

公开(公告)日：1989-08-01

申请号：US253986

申请日：1988-10-05

Applicant: Peter R. Chant

Inventor： Peter R. Chant

IPC: H05K3/18 ,  H05K3/10 ,  H05K3/22 ,  H05K3/38

CPC classification number: H05K3/107 ,  H05K3/387 ,  H05K2201/0133 ,  H05K2201/0376 ,  H05K2203/0278 ,  H05K2203/066 ,  H05K2203/095 ,  H05K2203/1105 ,  H05K3/108 ,  H05K3/181 ,  H05K3/388 ,  Y10S428/901 ,  Y10T29/49155 ,  Y10T428/12396 ,  Y10T428/24917 ,  Y10T428/31522

Abstract: A process for producing circuit boards involves the coating of a temporary substrate with a fluid mixture of an epoxy polymer component and a rubber polymer which is interactive therewith at temperatures of at least 180.degree. F. Preferably the rubber is a low molecular weight polyfunctional reactive butadiene/acrylonitrile interpolymer which is terminated by vinyl or carboxyl functional groups. The rubber component comprises at least 70 percent by weight of the epoxy polymer component, and the coating has a thickness of 0.001-0.015 inch. The coating is air dried upon the temporary substrate, and then the coating is transferred to the resinous substrate of the circuit board by heat and pressure. The coating is partially cured to effect partial polymerization of the epoxy prepolymer, further polymerization of the rubber, if it is of low molecular weight, and interaction of the rubber and epoxy polymer to form a matrix of the interacted rubber/epoxy. The exposed surface of this coating is then etched, and metal is deposited on the surface to form a conductive layer. A conductive pattern is formed therein, and heat and pressure is applied to at least the conductive layer and coating to fully cure the coating and bond the coating to the conductive layer, and thus the conductive pattern to the resinous substrate. The metal layer may be deposited chemically or by vacuum metallizing and like techniques.

Abstract translation: 制造电路板的方法包括用至少180°F的温度下与环氧聚合物组分和橡胶聚合物的流体混合物涂覆临时衬底。优选地，橡胶是低分子量多官能活性丁二烯 /丙烯腈互聚物，其由乙烯基或羧基官能团封端。 橡胶组分包含至少70重量％的环氧聚合物组分，并且涂层具有0.001-0.015英寸的厚度。 将涂层在临时基板上空气干燥，然后通过热和压力将涂层转移到电路板的树脂基板。 涂层被部分固化以实现环氧预聚物的部分聚合，如果其分子量低，橡胶的进一步聚合，以及橡胶与环氧聚合物的相互作用形成相互作用的橡胶/环氧树脂的基体。 然后蚀刻该涂层的暴露表面，并将金属沉积在表面上以形成导电层。 在其中形成导电图案，并且至少对导电层和涂层施加热和压力，以使涂层完全固化，并将涂层粘合到导电层上，从而将导电图案粘合到树脂基材上。 金属层可以化学沉积或通过真空金属化和类似的技术沉积。

公开(公告)号：US4631100A

公开(公告)日：1986-12-23

申请号：US671672

申请日：1984-11-15

Applicant: Peter P. Pellegrino

Inventor： Peter P. Pellegrino

IPC: H05K1/00 ,  H05K3/06 ,  H05K3/42 ,  H05K3/46 ,  C25D7/00 ,  B05D5/00 ,  B44C1/22 ,  C23F1/02

CPC classification number: H05K3/46 ,  H05K1/0287 ,  H05K3/429 ,  H05K1/0298 ,  H05K2201/0376 ,  H05K2201/09454 ,  H05K2201/09718 ,  H05K2201/09945 ,  H05K2203/107 ,  H05K2203/175 ,  H05K3/06 ,  Y10S428/901 ,  Y10T29/49156 ,  Y10T29/49158 ,  Y10T428/12396

Abstract: The present invention contemplates fabrication of a printed circuit board blank having a predetermined pattern of pads and interconnecting conductive pathways, preferably (but not necessarily) flush with the face of the insulating substrate. To fabricate a finished circuit board of any desired circuit configuration, the printed circuit board blank is coated with a photoresist and exposed so that upon development of the photoresist and etching in accordance with the developed pattern, the interconnecting conductive pathways between pads will be selectively etched away so that only those interconnects for the desired circuit pattern remain. While contact printing or image exposure systems may be used to expose the photoresist, computer controlled raster scan laser printers offer the combination of speed and versatility, as the predetermined starting matrix of the invention is highly conductive to computer aided design, and the percentage of circuit board area required for exposure is very small compared to normal copper-clad board fabrication techniques. For multilayer printed circuit boards, registration apertures are provided in each board layer for alignment purposes. Interconnects between boards are made by drilling through selective pads and plating the through holes to interconnect the various board layers. Isolation of any layer of any plated through hole may be obtained by either isolation of the pad (removal of all pad interconnects) at the through hole, or alternatively by etching a larger diameter in the pad which region will be filled with laminating adhesive during the lamination process to insulate the pad from the through hole copper plating.

Abstract translation: 本发明考虑制造具有预定图案的焊盘和互连导电路径的印刷电路板坯料，优选（但不一定）与绝缘衬底的表面齐平。 为了制造任何所需电路结构的成品电路板，印刷电路板坯体被涂覆有光致抗蚀剂并暴露，使得在显影光刻胶和根据显影图案进行蚀刻时，焊盘之间的互连导电路径将被选择性地蚀刻 使得仅保留用于所需电路图案的那些互连。 尽管接触式印刷或图像曝光系统可用于曝光光致抗蚀剂，但计算机控制的光栅扫描激光打印机提供速度和多功能性的组合，因为本发明的预定起始矩阵对于计算机辅助设计是高度导电的，并且电路的百分比 与正常的铜包覆板制造技术相比，曝光所需的板面积非常小。 对于多层印刷电路板，在每个板层中设置配准孔用于对准目的。 板之间的互连是通过选择性焊盘钻孔和电镀通孔来互连各个板层而制成的。 任何电镀通孔的任何层的隔离可以通过在通孔处隔离焊盘（去除所有焊盘互连）来获得，或者通过蚀刻焊盘中的较大直径来获得，该区域将在层压粘合剂期间填充层压粘合剂 层压工艺使焊盘与通孔镀铜绝缘。

公开(公告)号：US4604678A

公开(公告)日：1986-08-05

申请号：US515008

申请日：1983-07-18

Applicant: George R. Hagner

Inventor： George R. Hagner

IPC: H01L23/538 ,  H05K1/02 ,  H05K1/05 ,  H05K1/18 ,  H05K3/00 ,  H05K3/10 ,  H05K3/18 ,  H05K3/32 ,  H05K7/06

CPC classification number: H05K7/06 ,  H01L23/538 ,  H05K1/183 ,  H05K3/107 ,  H01L2924/0002 ,  H05K1/0203 ,  H05K1/021 ,  H05K1/0263 ,  H05K1/056 ,  H05K2201/0376 ,  H05K2201/09036 ,  H05K2201/09118 ,  H05K2201/098 ,  H05K2201/10636 ,  H05K2203/1461 ,  H05K2203/1469 ,  H05K3/0032 ,  H05K3/0061 ,  H05K3/108 ,  H05K3/181 ,  H05K3/32 ,  Y02P70/611

Abstract: An improved circuit board having electrically conductive traces connected to respective terminals of a number of electrically current components mounted on a substrate. The substrate has cavities for mounting the components, and a plurality of grooves extend into one or both of a pair of opposed surfaces of the substrate. The grooves are filled by plating with an electrically conductive material to form the traces. Thus, the traces not only extend in the plane of a surface of the substrate but also extend perpendicular to such plane and into the substrate itself whereby a high packing density of traces can be achieved while maintaining essentially electrical paths between the components. The depth of each trace is a number of times greater than the width of the trace, a typical ratio being 10:1. The substrate can be molded from a plateable plastic or ceramic material and the grooves can be machined by a laser beam. The components are assembled before the grooves are plated to minimize production costs and to assure immediate electrical connection between the tracers and the terminals of respective components.

Abstract translation: 一种改进的电路板，其具有连接到安装在基板上的多个电流部件的相应端子的导电迹线。 衬底具有用于安装部件的空腔，并且多个凹槽延伸到衬底的一对相对表面中的一个或两个中。 通过用导电材料电镀填充凹槽以形成迹线。 因此，迹线不仅在衬底的表面的平面中延伸，而且还垂直于这种平面延伸并延伸到衬底本身中，由此可以在保持组件之间的基本电路的同时实现高填充密度的迹线。 每个迹线的深度比轨迹的宽度大一倍，典型的比例为10：1。 衬底可以由可压片的塑料或陶瓷材料模制，并且可以通过激光束来加工凹槽。 在凹槽被镀覆之前组件被组装以最小化生产成本并且确保示踪器和各个部件的端子之间的即时电连接。

公开(公告)号：US4532152A

公开(公告)日：1985-07-30

申请号：US512461

申请日：1983-07-11

Applicant: Vito D. Elarde

Inventor： Vito D. Elarde

IPC: H05K3/04 ,  H05K3/06 ,  H05K3/10 ,  H05K3/14 ,  H05K3/18 ,  H05K3/38 ,  H05K3/42 ,  B05D5/12

CPC classification number: H05K3/045 ,  H05K3/107 ,  H05K3/108 ,  H05K3/14 ,  H05K3/181 ,  H05K2201/0376 ,  H05K2201/09036 ,  H05K2201/09118 ,  H05K2203/025 ,  H05K2203/1344 ,  H05K3/061 ,  H05K3/062 ,  H05K3/388 ,  H05K3/427 ,  Y10T29/49158 ,  Y10T29/4916

Abstract: A plastic substrate is injection molded to provide a pattern of channels in at least one of its sides to define a predetermined set of conductive paths. Both the surfaces of the channels and the non-channel surfaces therebetween are metalling through one or more steps of flame spraying, a combination of electroless plating and electroplating, gas plating or vacuum deposition. In one form of the invention the metallization over the non-channel surfaces is removed by abrading. In another form of the invention the initial metallization over the non-channel surfaces is coated with a resist prior to the deposition of another metal layer. The metal covering the channels is subsequently removed by stripping the resist and etching away the initial metallization.

Abstract translation: 注塑塑料基板以在其至少一个侧面提供通道图案，以限定一组预定的导电路径。 通道和非通道表面之间的两个表面均通过一个或多个火焰喷涂步骤，化学镀和电镀，气镀或真空沉积的组合进行金属化。 在本发明的一种形式中，非沟道表面上的金属化通过研磨去除。 在本发明的另一种形式中，非沟道表面上的初始金属化在另一金属层沉积之前被抗蚀剂涂覆。 随后通过剥离抗蚀剂去除覆盖通道的金属，并蚀刻掉初始金属化。

公开(公告)号：US4521262A

公开(公告)日：1985-06-04

申请号：US439333

申请日：1983-01-10

Applicant: Peter P. Pellegrino

Inventor： Peter P. Pellegrino

IPC: H05K1/00 ,  H05K1/11 ,  H05K3/06 ,  H05K3/42 ,  C25D7/00 ,  B05D5/00 ,  B44C1/22 ,  C23F1/02

CPC classification number: H05K3/429 ,  H05K1/0287 ,  H05K1/029 ,  H05K1/116 ,  H05K1/0298 ,  H05K2201/0376 ,  H05K2201/09454 ,  H05K2201/09718 ,  H05K2201/09945 ,  H05K2203/107 ,  H05K2203/175 ,  H05K3/06 ,  Y10T29/49165

Abstract: The present invention contemplates fabrication of a printed circuit board blank having a predetermined pattern of pads and interconnecting conductive pathways, preferably (but not necessarily) flush with the face of the insulating substrate. To fabricate a finished circuit board of any desired circuit configuration, the printed circuit board blank is coated with a photoresist and exposed so that upon development of the photoresist and etching in accordance with the developed pattern, the interconnecting conductive pathways between pads will be selectively etched away so that only those interconnects for the desired circuit pattern remain. While contact printing or image exposure systems may be used to expose the photoresist, computer controlled raster scan laser printers offer the combination of speed and versatility, as the predetermined starting matrix of the invention is highly conducive to computer aided design, and the percentage of circuit board area required for exposure is very small compared to normal copper-clad board fabrication techniques. For multilayer printed circuit boards, registration apertures are provided in each board layer for alignment purposes. Interconnects between boards are made by drilling through selective pads and plating the through holes to interconnect the various board layers. Isolation of any layer of any plated through hole may be obtained by either isolation of the pad (removal of all pad interconnects) at the through hole, or alternatively by etching a larger diameter in the pad which region will be filled with laminating adhesive during the lamination process to insulate the pad from the through hole copper plating.

Abstract translation: 本发明考虑制造具有预定图案的焊盘和互连导电路径的印刷电路板坯料，优选（但不一定）与绝缘衬底的表面齐平。 为了制造任何所需电路结构的成品电路板，印刷电路板坯体被涂覆有光致抗蚀剂并暴露，使得在显影光刻胶和根据显影图案进行蚀刻时，焊盘之间的互连导电路径将被选择性地蚀刻 使得仅保留用于所需电路图案的那些互连。 虽然接触式印刷或图像曝光系统可用于曝光光致抗蚀剂，但是由于本发明的预定起始矩阵高度有利于计算机辅助设计，所以计算机控制的光栅扫描激光打印机提供了速度和多功能性的组合，并且电路的百分比 与正常的铜包覆板制造技术相比，曝光所需的板面积非常小。 对于多层印刷电路板，在每个板层中设置配准孔用于对准目的。 板之间的互连是通过选择性焊盘钻孔和电镀通孔来互连各个板层而制成的。 任何电镀通孔的任何层的隔离可以通过在通孔处隔离焊盘（去除所有焊盘互连）来获得，或者通过蚀刻焊盘中的较大直径来获得，该区域将在层压粘合剂期间填充层压粘合剂 层压工艺使焊盘与通孔镀铜绝缘。