公开(公告)号：US06623651B2

公开(公告)日：2003-09-23

申请号：US09815364

申请日：2001-03-22

Applicant: Bharat Patel ,  Jay D. Baker ,  Mohan Paruchuri

Inventor： Bharat Patel ,  Jay D. Baker ,  Mohan Paruchuri

IPC: H01B1300

CPC classification number: H05K3/44 ,  H05K3/0047 ,  H05K3/06 ,  H05K3/062 ,  H05K3/064 ,  H05K3/4038 ,  H05K3/4069 ,  H05K3/429 ,  H05K3/445 ,  H05K3/4608 ,  H05K3/4611 ,  H05K3/4614 ,  H05K3/462 ,  H05K3/4623 ,  H05K3/4641 ,  H05K3/4647 ,  H05K3/4652 ,  H05K3/4685 ,  H05K2201/0305 ,  H05K2201/0352 ,  H05K2201/0355 ,  H05K2201/0361 ,  H05K2201/0379 ,  H05K2201/0397 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09554 ,  H05K2201/09609 ,  H05K2201/09845 ,  H05K2201/09881 ,  H05K2203/0369 ,  H05K2203/066 ,  H05K2203/0733 ,  H05K2203/1152 ,  H05K2203/1184 ,  H05K2203/1536

Abstract: A method 10 for making a multi-layer electronic circuit board 98 having at least one electrically conductive protuberance 15 which forms a “via” and which traverses through the various layers of the electric circuit board 98, and further having at least one interconnection portion 102 which supports a wide variety of components and interconnection assemblies.

Abstract translation: 一种用于制造多层电子电路板98的方法10，该多层电子电路板98具有形成“通孔”的至少一个导电突起15，并穿过电路板98的各个层，并且还具有至少一个互连部分102 其支持各种组件和互连组件。

公开(公告)号：US20030121146A1

公开(公告)日：2003-07-03

申请号：US10239731

申请日：2002-11-14

Inventor： Walter Schmidt

IPC: H05K003/02 ,  H05K003/10

CPC classification number: H01L23/49827 ,  H01L2924/0002 ,  H05K1/0263 ,  H05K1/0268 ,  H05K1/0272 ,  H05K1/0274 ,  H05K1/113 ,  H05K1/115 ,  H05K1/141 ,  H05K1/144 ,  H05K1/162 ,  H05K1/185 ,  H05K3/005 ,  H05K3/0055 ,  H05K3/0061 ,  H05K3/041 ,  H05K3/046 ,  H05K3/3436 ,  H05K3/368 ,  H05K3/4084 ,  H05K3/4602 ,  H05K3/4614 ,  H05K3/4641 ,  H05K3/4644 ,  H05K3/4652 ,  H05K2201/0379 ,  H05K2201/0394 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09527 ,  H05K2201/09636 ,  H05K2201/0969 ,  H05K2201/09827 ,  H05K2201/10378 ,  H05K2201/10598 ,  H05K2203/0108 ,  H05K2203/0195 ,  H05K2203/0285 ,  H05K2203/095 ,  H05K2203/1189 ,  H05K2203/163 ,  Y02P70/613 ,  Y10T29/49155 ,  H01L2924/00

Abstract: According to the invention, a microperforation (PMP) process step is combined with the lamination process. To this end, a dielectric layer are and a prefabricated product are placed between a support and a perforation die. The prefabricated product is partially covered by a conducting layer forming structures to be contacted by microvias. Pressure is applied on the perforation die, perforation tips of the perforation die forming microvias for contacting the structures. A surface of the dielectric layer or the prefabricated product is configured or coated to in a manner that the prefabricated product and the dielectric layer stick to each other after the pressure has been applied.

Abstract translation: 根据本发明，将微穿孔（PMP）工艺步骤与层压工艺组合。 为此，介电层和预制产品被放置在支撑件和穿孔模具之间。 预制产品被形成由微孔接触的结构的导电层部分覆盖。 在穿孔模具上施加压力，穿孔模具的穿孔尖端形成用于接触结构的微孔。 在施加压力之后，电介质层或预制产品的表面被构造或涂覆成使得预制产品和电介质层彼此粘合。

公开(公告)号：US20030102466A1

公开(公告)日：2003-06-05

申请号：US09779480

申请日：2001-02-09

Applicant: SONY CHEMICALS CORP.

Inventor： Hiroyuki Kumakura ,  Satoshi Yamamoto

IPC: H01B001/22

CPC classification number: H01L24/83 ,  C08L63/00 ,  C09J7/10 ,  C09J9/02 ,  C09J2201/36 ,  C09J2201/602 ,  C09J2433/00 ,  C09J2463/00 ,  H01B1/22 ,  H01B3/18 ,  H01L24/29 ,  H01L2224/16225 ,  H01L2224/2919 ,  H01L2224/73204 ,  H01L2224/83101 ,  H01L2224/8319 ,  H01L2224/838 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01045 ,  H01L2924/01047 ,  H01L2924/01055 ,  H01L2924/0132 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/0781 ,  H01L2924/07811 ,  H01L2924/14 ,  H01R4/04 ,  H05K3/323 ,  H05K2201/0133 ,  H05K2201/0379 ,  H05K2201/10674 ,  H05K2203/1189 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49155 ,  Y10T29/49211 ,  Y10T156/1052 ,  Y10T428/254 ,  Y10T428/269 ,  Y10T428/2857 ,  Y10T428/2991 ,  Y10T428/2998 ,  H01L2924/00 ,  H01L2924/01028

Abstract: An anisotropic conductive adhesive film contains a first insulating adhesive layer, a second insulating adhesive layer whose modulus of elasticity after curing is less than the modulus of elasticity of the cured first insulating adhesive layer, and electrically conductive particles which are dispersed in at least either the first insulating adhesive layer or the second insulating adhesive layer.

Abstract translation: 各向异性导电粘合剂膜包含第一绝缘粘合剂层，固化后的弹性模量小于固化的第一绝缘粘合剂层的弹性模量的第二绝缘粘合剂层和分散在至少 第一绝缘粘合剂层或第二绝缘粘合剂层。

公开(公告)号：US20030034174A1

公开(公告)日：2003-02-20

申请号：US10198341

申请日：2002-07-18

Inventor： Zhong-You Shi ,  Delin Li ,  Richard McMillan

IPC: H05K003/20 ,  H01R012/04

CPC classification number: H05K3/429 ,  H05K3/0047 ,  H05K3/06 ,  H05K3/062 ,  H05K3/064 ,  H05K3/4038 ,  H05K3/4069 ,  H05K3/44 ,  H05K3/445 ,  H05K3/4608 ,  H05K3/4611 ,  H05K3/4623 ,  H05K3/4641 ,  H05K3/4685 ,  H05K2201/0305 ,  H05K2201/0352 ,  H05K2201/0355 ,  H05K2201/0361 ,  H05K2201/0379 ,  H05K2201/0397 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09554 ,  H05K2201/09563 ,  H05K2201/09609 ,  H05K2201/09845 ,  H05K2201/09881 ,  H05K2203/0369 ,  H05K2203/066 ,  H05K2203/0733 ,  H05K2203/1152 ,  H05K2203/1184 ,  H05K2203/1536 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165 ,  Y10T428/24917

Abstract: A method 10, 110 for making multi-layer circuit boards having metallized apertures 38, 40, 130, 132 which may be selectively and electrically grounded and having at least one formed air-bridge 92, 178.

Abstract translation: 一种用于制造具有金属化孔38,40,130,132的多层电路板的方法10,110，其可以选择性地和电接地并且具有至少一个形成的空气桥92,178。

公开(公告)号：US06465082B1

公开(公告)日：2002-10-15

申请号：US09554502

申请日：2000-05-16

Applicant: Hiroaki Takezawa ,  Masahide Tsukamoto ,  Minehiro Itagaki ,  Yoshihiro Bessho ,  Hideo Hatanaka ,  Yasushi Fukumura ,  Kazuo Eda ,  Toru Ishida

Inventor： Hiroaki Takezawa ,  Masahide Tsukamoto ,  Minehiro Itagaki ,  Yoshihiro Bessho ,  Hideo Hatanaka ,  Yasushi Fukumura ,  Kazuo Eda ,  Toru Ishida

IPC: H05K100

CPC classification number: H05K3/3436 ,  H01L23/49816 ,  H01L2224/16225 ,  H05K1/0271 ,  H05K3/105 ,  H05K3/321 ,  H05K2201/0212 ,  H05K2201/0379 ,  H05K2201/10257 ,  H05K2201/10992 ,  H05K2203/121 ,  Y02P70/613 ,  Y10S428/901 ,  Y10T428/24917 ,  Y10T428/254 ,  Y10T428/31681

Abstract: A stress relaxation type electronic component which is to be mounted on a circuit board, wherein a stress relaxation mechanism member is disposed on a surface of said electronic component, said surface being on a side of a connection portion where said electronic component is to be connected to said circuit board, and said stress relaxation mechanism member is electrically conductive.

Abstract translation: 一种要安装在电路板上的应力松弛型电子部件，其中应力松弛机构部件设置在所述电子部件的表面上，所述表面位于要连接所述电子部件的连接部分的一侧 到所述电路板，并且所述应力松弛机构构件是导电的。

公开(公告)号：US06449839B1

公开(公告)日：2002-09-17

申请号：US09655986

申请日：2000-09-06

Applicant: Andrew Z. Glovatsky ,  Thomas Krautheim ,  Robert E. Belke, Jr. ,  Vivek Amir Jairazbhoy ,  Cuong V. Pham

Inventor： Andrew Z. Glovatsky ,  Thomas Krautheim ,  Robert E. Belke, Jr. ,  Vivek Amir Jairazbhoy ,  Cuong V. Pham

IPC: H05K302

CPC classification number: H05K3/4084 ,  H05K1/056 ,  H05K3/062 ,  H05K3/4092 ,  H05K3/44 ,  H05K3/445 ,  H05K2201/0305 ,  H05K2201/0361 ,  H05K2201/0379 ,  H05K2201/0397 ,  H05K2201/09554 ,  H05K2203/0195 ,  H05K2203/063 ,  Y10T29/49128 ,  Y10T29/49144 ,  Y10T29/49156

Abstract: A method for forming connections within a multi-layer electronic circuit board 10. In one non-limiting embodiment, the method includes selectively forming air bridges over portions of the circuit board 10 and selectively collapsing the air bridges with a metallurgical bonding tool, effective to interconnect layers of the circuit board 10.

Abstract translation: 一种用于在多层电子电路板10内形成连接的方法。在一个非限制性实施例中，该方法包括在电路板10的部分上选择性地形成空气桥，并用冶金接合工具选择性地折叠气桥， 电路板10的互连层。

公开(公告)号：US06426566B1

公开(公告)日：2002-07-30

申请号：US09601033

申请日：2000-07-26

Applicant: Toshihiro Sawamoto

Inventor： Toshihiro Sawamoto

IPC: H01L2348

CPC classification number: H01L24/31 ,  H01L23/49827 ,  H01L24/29 ,  H01L24/83 ,  H01L2224/04026 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29299 ,  H01L2224/293 ,  H01L2224/2939 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/83101 ,  H01L2224/83192 ,  H01L2224/838 ,  H01L2224/83851 ,  H01L2224/83951 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0665 ,  H01L2924/0781 ,  H01L2924/07811 ,  H01L2924/15787 ,  H05K3/323 ,  H05K2201/0379 ,  H05K2201/10674 ,  H05K2203/1189 ,  H01L2924/00 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/05599

Abstract: An anisotropic conductive film 3 bonds the semiconductor chip 1 to the substrate 2 while serving as an electrically conductive medium therebetween. The anisotropic conductive film 3 is produced by laminating, in a unitary body, an electrically conductive particle containing layer 31 constructed of a mixture of electrically conductive particles and a resin, and an electrically non-conductive layer 32 having a fluidity lower than the fluidity of the electrically conductive particle containing layer.

Abstract translation: 各向异性导电膜3将半导体芯片1与基板2连接起来，同时用作它们之间的导电介质。 各向异性导电膜3通过在整体上层叠由导电粒子和树脂的混合物构成的导电性粒子层31和流动性低于流动性的导电性层32而制造 导电性粒子含有层。

公开(公告)号：US06424037B1

公开(公告)日：2002-07-23

申请号：US09941384

申请日：2001-08-28

Applicant: Chung W Ho ,  Tsing-Chow Wang

Inventor： Chung W Ho ,  Tsing-Chow Wang

IPC: H01L2348

CPC classification number: H01L24/12 ,  H01L21/4853 ,  H01L23/49816 ,  H01L24/11 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05671 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13583 ,  H01L2224/136 ,  H01L2224/13647 ,  H01L2224/13671 ,  H01L2224/81801 ,  H01L2924/00013 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01054 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H05K3/3436 ,  H05K2201/0379 ,  H05K2201/1025 ,  H05K2201/2081 ,  H05K2203/0315 ,  Y02P70/613 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2224/29099 ,  H01L2924/00

Abstract: Within a method for forming a solder interconnection structure for use within a microelectronic fabrication, there is first provided a substrate having formed thereover a bond pad. There is then formed upon the bond pad a first solder interconnection layer. There is then formed over the first solder interconnection layer an annular solder non-wettable copper oxide layer which does not cover an upper dome portion of the first solder interconnection layer. There is then formed over the upper dome portion of the first solder interconnection layer and not upon the annular solder non-wettable copper oxide layer a second solder interconnection layer.

公开(公告)号：US20020015340A1

公开(公告)日：2002-02-07

申请号：US09915708

申请日：2001-07-25

Inventor： Victor Batinovich

IPC: G11C029/00

CPC classification number: H01L25/0657 ,  G11C5/04 ,  G11C29/06 ,  H01L21/4853 ,  H01L23/49816 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/48 ,  H01L24/94 ,  H01L2224/05599 ,  H01L2224/11334 ,  H01L2224/1191 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/16 ,  H01L2224/274 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/854 ,  H01L2225/06551 ,  H01L2225/06572 ,  H01L2225/06579 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/181 ,  H05K3/3436 ,  H05K2201/0379 ,  H05K2201/10977 ,  H05K2203/025 ,  Y02P70/613 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012

Abstract: An IC package for mounting to a surface of a device board includes a first IC having a first surface supporting a first plurality of conductive leads extending orthogonally from the first surface, a second IC having a second surface supporting a second plurality of conductive leads extending orthogonally from the second surface, the first and second ICs spaced apart in parallel with the first and second surfaces facing, and an interposer trace board parallel to the first and second ICs and positioned between the first and second ICs, the trace board having conducting metal traces on a non-conductive sheet material, the traces accessible from both sides of the trace board, being exposed at selected regions through the non-conductive sheet. The package is characterized in that the conductive traces contact individual ones of the first and second pluralities of conductive leads, providing conductive signal paths from the first and second ICs between the ICs and leading to edges of the IC package.

Abstract translation: 用于安装到器件板表面的IC封装包括第一IC，其具有支撑从第一表面正交延伸的第一多个导电引线的第一表面，具有第二表面的第二IC，第二表面支撑正交延伸的第二多个导电引线 从第二表面开始，第一和第二IC与第一和第二表面平行间隔开，并且插入器跟踪板平行于第一和第二IC并定位在第一和第二IC之间，迹线板具有导电金属迹线 在非导电片材上，可从迹线板的两侧接近的迹线通过非导电片暴露在选定区域。 封装的特征在于，导电迹线接触第一和第二多个导电引线中的多个导电引线，从IC之间的第一和第二IC提供导电信号路径并且引导到IC封装的边缘。

公开(公告)号：US06344695B1

公开(公告)日：2002-02-05

申请号：US09414503

申请日：1999-10-08

Applicant: Kei Murayama

Inventor： Kei Murayama

IPC: H01L2348

CPC classification number: H05K3/3436 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/11334 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2924/0001 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/07802 ,  H05K2201/0379 ,  H05K2201/09472 ,  H05K2201/10992 ,  H05K2203/043 ,  Y02P70/613 ,  H01L2924/0105 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A semiconductor chip has an active surface with electrodes thereon and an insulating layer covering the active surface and having through holes therein through which corresponding electrodes are exposed. Rewiring circuits are formed on the insulating layer, each having a first terminal end extending through a corresponding through hole and electrically connected to a respective electrode and a second terminal end comprising a conductive pad. Respective inner bumps are formed on the second terminal ends of the rewiring circuits. An insulating film is formed on the rewiring circuits and exposed surfaces of the insulating layer and through holes are formed therein corresponding to the conductive pads and into which respective inner bumps are inserted. A respective outer bump is superimposed on each inner bump in the insulating film and projects beyond an exposed surface of the insulating film remote from the semiconductor chip. In an alternative, inner bumps are omitted and the outer bumps are directly superimposed on the conductive pads in the corresponding through holes. A method of making the semiconductor device provides for superimposing outer bumps either directly on the respective conductive pads in the corresponding through holes, where inner bumps are not employed, or superimposing same on the respective inner bumps after superimposing the inner bumps on the respective conductive pads.

Abstract translation: 半导体芯片具有其上具有电极的活性表面和覆盖有源表面的绝缘层，并且在其中具有通孔，相应的电极通过该孔暴露。 重叠电路形成在绝缘层上，每个具有延伸穿过相应通孔并且电连接到相应电极的第一端部和包括导电焊盘的第二端子。 在再布线电路的第二端部形成有各自的内部凸点。 在再布线电路上形成绝缘膜，绝缘层的露出表面形成有与导电焊盘相对应的通孔，并且插入有各自的内凸块。 相应的外部凸起叠加在绝缘膜的每个内部凸起上，并突出超过远离半导体芯片的绝缘膜的暴露表面。 另一方面，省略了内部凸块，并且外部凸块直接叠加在相应通孔中的导电焊盘上。 制造半导体器件的方法提供了将外部凸块直接叠加在不使用内部凸起的相应通孔中的相应导电焊盘上，或者将内部凸块叠加在各个导电焊盘上之后将其叠加在相应的内部凸起上 。