公开(公告)号：US06623651B2

公开(公告)日：2003-09-23

申请号：US09815364

申请日：2001-03-22

Applicant: Bharat Patel ,  Jay D. Baker ,  Mohan Paruchuri

Inventor： Bharat Patel ,  Jay D. Baker ,  Mohan Paruchuri

IPC: H01B1300

CPC classification number: H05K3/44 ,  H05K3/0047 ,  H05K3/06 ,  H05K3/062 ,  H05K3/064 ,  H05K3/4038 ,  H05K3/4069 ,  H05K3/429 ,  H05K3/445 ,  H05K3/4608 ,  H05K3/4611 ,  H05K3/4614 ,  H05K3/462 ,  H05K3/4623 ,  H05K3/4641 ,  H05K3/4647 ,  H05K3/4652 ,  H05K3/4685 ,  H05K2201/0305 ,  H05K2201/0352 ,  H05K2201/0355 ,  H05K2201/0361 ,  H05K2201/0379 ,  H05K2201/0397 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09554 ,  H05K2201/09609 ,  H05K2201/09845 ,  H05K2201/09881 ,  H05K2203/0369 ,  H05K2203/066 ,  H05K2203/0733 ,  H05K2203/1152 ,  H05K2203/1184 ,  H05K2203/1536

Abstract: A method 10 for making a multi-layer electronic circuit board 98 having at least one electrically conductive protuberance 15 which forms a “via” and which traverses through the various layers of the electric circuit board 98, and further having at least one interconnection portion 102 which supports a wide variety of components and interconnection assemblies.

Abstract translation: 一种用于制造多层电子电路板98的方法10，该多层电子电路板98具有形成“通孔”的至少一个导电突起15，并穿过电路板98的各个层，并且还具有至少一个互连部分102 其支持各种组件和互连组件。

公开(公告)号：US06082610A

公开(公告)日：2000-07-04

申请号：US880955

申请日：1997-06-23

Applicant: Dongkai Shangguan ,  Mohan Paruchuri ,  Achyuta Achari

Inventor： Dongkai Shangguan ,  Mohan Paruchuri ,  Achyuta Achari

IPC: H01L23/12 ,  H01L21/60 ,  H01L23/485 ,  H01L23/498 ,  H05K3/34 ,  B23K1/20 ,  H01L21/441 ,  H01L29/40

CPC classification number: H01L24/10 ,  H01L23/49866 ,  H01L24/13 ,  H01L24/81 ,  H05K3/3463 ,  H01L2224/05001 ,  H01L2224/05023 ,  H01L2224/0508 ,  H01L2224/05184 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/13109 ,  H01L2224/13144 ,  H01L2224/81801 ,  H01L2924/00013 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15747 ,  H01L2924/30107 ,  Y10T29/49144

Abstract: A method which utilizes flip chip technology to provide interconnection between printed circuit boards and integrated circuits is disclosed. The method involves metallization of the bond pad and multiple, novel bump compositions and coating compositions to provide an interconnection which is reliable and which withstands differences in the coefficient of thermal expansion between the silicon device and the bump material.

Abstract translation: 公开了一种利用倒装芯片技术提供印刷电路板和集成电路之间的互连的方法。 该方法涉及金属化接合焊盘和多个新颖的凸块组合物和涂层组合物，以提供可靠的互连，并且能够承受硅器件和凸块材料之间的热膨胀系数的差异。

公开(公告)号：US06250541B1

公开(公告)日：2001-06-26

申请号：US09553909

申请日：2000-04-20

Applicant: Dongkai Shangguan ,  Mohan Paruchuri ,  Achyuta Achari

Inventor： Dongkai Shangguan ,  Mohan Paruchuri ,  Achyuta Achari

IPC: B23K3102

CPC classification number: H01L24/10 ,  H01L23/49866 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/05001 ,  H01L2224/05023 ,  H01L2224/0508 ,  H01L2224/05184 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/13109 ,  H01L2224/13144 ,  H01L2224/81801 ,  H01L2924/00013 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15747 ,  H01L2924/30107 ,  H05K3/3463 ,  Y10T29/49144 ,  H01L2224/29099 ,  H01L2924/00 ,  H01L2224/05639 ,  H01L2924/00014 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166

Abstract: A method which utilizes flip chip technology to provide interconnection between printed circuit boards and integrated circuits is disclosed. The method involves metallization of the bond pad and multiple, novel bump compositions and coating compositions to provide an interconnection which is reliable and which withstands differences in the coefficient of thermal expansion between the silicon device and the bump material.

Abstract translation: 公开了一种利用倒装芯片技术提供印刷电路板和集成电路之间的互连的方法。 该方法涉及金属化接合焊盘和多个新颖的凸块组合物和涂层组合物，以提供可靠的互连，并且能够承受硅器件和凸块材料之间的热膨胀系数的差异。

公开(公告)号：US6011313A

公开(公告)日：2000-01-04

申请号：US241885

申请日：1999-02-01

Applicant: Dongkai Shangguan ,  Mohan Paruchuri ,  Achyuta Achari

Inventor： Dongkai Shangguan ,  Mohan Paruchuri ,  Achyuta Achari

IPC: H01L23/12 ,  H01L21/60 ,  H01L23/485 ,  H01L23/498 ,  H05K3/34 ,  H01L23/48

CPC classification number: H01L24/10 ,  H01L23/49866 ,  H01L24/13 ,  H01L24/81 ,  H05K3/3463 ,  H01L2224/05001 ,  H01L2224/05023 ,  H01L2224/0508 ,  H01L2224/05184 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/13109 ,  H01L2224/13144 ,  H01L2224/81801 ,  H01L2924/00013 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15747 ,  H01L2924/30107 ,  Y10T29/49144

Abstract: A device which utilizes flip chip technology to provide interconnection between printed circuit boards and integrated circuits is disclosed. The method involves metallization of the bond pad and multiple, novel bump compositions and coating compositions to provide an interconnection which is reliable and which withstands differences in the coefficient of thermal expansion between the silicon device and the bump material.

Abstract translation: 公开了一种使用倒装芯片技术来提供印刷电路板和集成电路之间的互连的装置。 该方法涉及金属化接合焊盘和多个新颖的凸块组合物和涂层组合物，以提供可靠的互连，并且能够承受硅器件和凸块材料之间的热膨胀系数的差异。

公开(公告)号：US06838623B2

公开(公告)日：2005-01-04

申请号：US10300049

申请日：2002-11-20

Applicant: Lawrence Kneisel ,  Mohan Paruchuri ,  Vivek Jairazboy ,  Vladimir Stoica

Inventor： Lawrence Kneisel ,  Mohan Paruchuri ,  Vivek Jairazboy ,  Vladimir Stoica

IPC: H05K3/38 ,  H05K3/40 ,  H05K3/44 ,  H05K3/46 ,  H05K1/03

CPC classification number: H05K3/4641 ,  H05K3/386 ,  H05K3/4038 ,  H05K3/445 ,  H05K2201/0195 ,  H05K2201/0305 ,  H05K2201/0361 ,  H05K2201/0397 ,  H05K2201/09554 ,  H05K2201/09581 ,  H05K2203/1438

Abstract: A multi-layer electronic circuit board design 10 having selectively formed apertures or cavities 26, and which includes grooves or troughs 20, 22 which are effective to selectively entrap liquefied adhesive material, thereby substantially preventing the adhesive material from entering the apertures 26.

公开(公告)号：US06620545B2

公开(公告)日：2003-09-16

申请号：US09755475

申请日：2001-01-05

Applicant: Lakhi N. Goenka ,  William F. Quilty, Jr. ,  Mohan Paruchuri

Inventor： Lakhi N. Goenka ,  William F. Quilty, Jr. ,  Mohan Paruchuri

IPC: H01M646

CPC classification number: H05K1/16 ,  H01M2/1022 ,  H01M2/1066

Abstract: A device for producing an electro-motive force is disclosed. The device includes a cover for creating a liquid seal, an electrolyte contained within the cover for creating an ionic transfer path (medium), and an etched tri-metal board (substrate). The etched tri-metal board has a first conductive layer, a second conductive layer and a third conductive layer. The first, second and third conductive layers are selectively etched to form a cathode and an anode. The cover is sealed against the substrate and filled with an electrolyte to form an electrical device, such as a battery.

公开(公告)号：US20050092478A1

公开(公告)日：2005-05-05

申请号：US10697839

申请日：2003-10-30

Applicant: Vivek Jairazbhoy ,  Mohan Paruchuri

Inventor： Vivek Jairazbhoy ,  Mohan Paruchuri

IPC: F28F13/00 ,  H01L23/373 ,  H01L23/473 ,  H05K1/02 ,  F28F7/00

CPC classification number: H05K1/0206 ,  F28F13/003 ,  H01L23/3733 ,  H01L23/473 ,  H01L2924/0002 ,  H05K2201/0116 ,  H05K2201/066 ,  H01L2924/00

Abstract: Further, a system is provided for dissipating heat from a semiconductor module including a semiconductor die and the unitary heat sink. The heat sink comprising a unitary body having both a porous and non-porous portion is provided. The non-porous portion is attached to the semiconductor die and configured to transfer heat to the porous portion for dissipation into the environment. In addition, a method for manufacturing the heat sink is provided.

Abstract translation: 此外，提供了一种用于从包括半导体管芯和整体散热器的半导体模块散热的系统。 提供了包括具有多孔和无孔部分的整体的散热器。 无孔部分附接到半导体管芯并且被配置为将热量传递到多孔部分以便耗散到环境中。 此外，还提供了制造散热器的方法。

公开(公告)号：US20050083655A1

公开(公告)日：2005-04-21

申请号：US10685931

申请日：2003-10-15

Applicant: Vivek Jairazbhoy ,  Prathap Reddy ,  Mohan Paruchuri ,  Jay Baker

Inventor： Vivek Jairazbhoy ,  Prathap Reddy ,  Mohan Paruchuri ,  Jay Baker

IPC: H01L23/373 ,  H01L23/427 ,  H01L23/473 ,  H05K7/20

CPC classification number: H01L23/3733 ,  H01L23/427 ,  H01L23/473 ,  H01L2224/48091 ,  H01L2224/49111 ,  H01L2224/49113 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2924/00014

Abstract: A system for dissipating heat in an electronic power module is provided. The system includes a semiconductor die, a substrate, and a heat sink in which is contained a first fluid, and a conduit through which a second fluid is permitted to flow. The substrate is attached on one surface to the die and configured to conduct heat from the die. The heat sink is attached to another surface of the substrate and transfers heat from the die to the first fluid contained therein, which evaporates due to the heat provided by the substrate. The fluid is condensed on a condensing wall cooled by the second fluid, which flows across the outer surface of the condensing wall, to transport heat away from the heat sink.

Abstract translation: 提供了一种用于在电子电源模块中散热的系统。 该系统包括半导体管芯，衬底和散热器，其中容纳有第一流体，以及允许第二流体流过的导管。 衬底在一个表面附着到管芯上，并被配置为从管芯传导热量。 散热器附接到基板的另一表面，并将热量从模具传递到其中包含的第一流体，由于由基板提供的热量而蒸发。 流体在由第二流体冷却的冷凝壁上冷凝，第二流体流过冷凝壁的外表面，以将热量从散热器传送出去。