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公开(公告)号：US20190200449A1
公开(公告)日：2019-06-27
申请号：US16174665
申请日：2018-10-30
Applicant: Japan Aviation Electronics Industry, Limited
Inventor： Kentaro TODA
IPC: H05K1/02
CPC classification number: H05K1/0222 , H01R12/53 , H01R12/722 , H05K1/0228 , H05K2201/09027 , H05K2201/09227 , H05K2201/09236 , H05K2201/09272 , H05K2201/09618
Abstract: A circuit board comprises at least a first wiring layer, a second wiring layer and a via. The first wiring layer is formed with a pair of first ends, a pair of second ends, a coupling portion, a pair of first trace portions and a pair of second trace portions. The coupling portion has a pair of first coupling points, a pair of second coupling points, an inner trace portion, an outer trace portion and a ground conductor portion. The inner trace portion has a length equal to a length of the outer trace portion. The ground conductor portion is arranged between the inner trace portion and the outer trace portion. The second wiring layer is formed with a ground pattern. The ground conductor portion is connected with the ground pattern through the via.
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公开(公告)号：US20180324939A1
公开(公告)日：2018-11-08
申请号：US15843031
申请日：2017-12-15
Applicant: BOE Technology Group Co., Ltd.
Inventor： Li Wang
CPC classification number: H05K1/028 , H01L27/1218 , H01L27/124 , H05K1/115 , H05K2201/09272 , H05K2201/10128 , H05K2201/10136
Abstract: Disclosed are a flexible display substrate, a display panel, and a display device. A traveling wire in a fixed bending area includes a plurality of sequentially connected wire segments at a preset inclination angle relative to the extension direction of the traveling wire, and furthermore hole structures are arranged on at least a part of the wire segments. Moreover there is a planar contact structure between at least two of wire segments connected with each other.
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公开(公告)号：US20180255638A1
公开(公告)日：2018-09-06
申请号：US15770281
申请日：2015-10-23
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Kevin B. Leigh , John Norton
CPC classification number: H05K1/11 , H04B10/40 , H05K1/0243 , H05K1/0295 , H05K1/141 , H05K1/181 , H05K2201/09236 , H05K2201/09272 , H05K2201/09954 , H05K2201/10121 , H05K2201/10378
Abstract: One example of a system includes a printed circuit board. The printed circuit board includes a switch chip footprint to receive a higher lane count switch chip or a lower lane count switch chip. The printed circuit board includes a plurality of transceiver module footprints. Each transceiver module footprint is electrically coupled to the switch chip footprint. Each transceiver module footprint may receive a higher lane count transceiver module or a lower lane count transceiver module.
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104.发明申请公开(公告)号：US20180138617A1
公开(公告)日：2018-05-17
申请号：US15351237
申请日：2016-11-14
Applicant: Microsoft Technology Licensing, LLC
CPC classification number: H01R12/91 , H01R12/721 , H01R12/78 , H04N13/344 , H04N2213/001 , H04N2213/008 , H05K1/0221 , H05K1/0295 , H05K1/11 , H05K3/361 , H05K2201/09272 , H05K2201/09381 , H05K2201/0939
Abstract: A universal coupling is disclosed for electrically and mechanically connecting flexible printed circuit (FPC) components within asymmetric FPC modules. The universal coupling allows a first FPC component to be connected to a second FPC component in two or more different orientations. This allows identical FPC components to be used in two or more asymmetric FPC modules. This in turn allows a reduction in the number of parts and tooling required to fabricate the two or more asymmetric FPC modules, and a simplification of the fabrication process.
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公开(公告)号：US20170290146A1
公开(公告)日：2017-10-05
申请号：US15463538
申请日：2017-03-20
Applicant: NITTO DENKO CORPORATION
Inventor： Yuu SUGIMOTO , Yoshito FUJIMURA , Hiroyuki TANABE
CPC classification number: H05K1/0284 , H05K1/0274 , H05K1/05 , H05K3/0008 , H05K3/06 , H05K3/064 , H05K3/108 , H05K3/4644 , H05K3/4679 , H05K2201/09227 , H05K2201/09272 , H05K2203/0557 , H05K2203/056 , H05K2203/0562
Abstract: A method of producing a wired circuit board including an insulating layer and a conductive pattern, including: (1), an insulating layer having an inclination face, (2), a metal thin film provided at least on the inclination face, (3), a photoresist provided on the surface of the metal thin film, (4), a light shield portion of a photomask disposed so that a first portion, where the conductive pattern is to be provided in the photoresist, is shielded from light, and the photoresist is exposed to light through the photomask, (5), the first portion of the photoresist is removed to expose the metal thin film corresponding to the first portion, and (6), the conductive pattern is provided on the surface of the metal thin film exposed from the photoresist.
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Patent Agency Ranking
公开(公告)号：US20170261799A1
公开(公告)日：2017-09-14
申请号：US15604877
申请日：2017-05-25
Applicant: SAMSUNG DISPLAY CO., LTD.
Inventor： CHONG-GUK LEE , JOO-YEON WON , SE-HUI JANG , SU-Ml MOON , DONG-WOOK LEE
IPC: G02F1/1345 , H01L23/498 , H01L27/12 , H05K1/02 , H01L23/00 , H05K1/18
CPC classification number: G02F1/13452 , H01L23/4985 , H01L24/16 , H01L24/48 , H01L27/124 , H01L2224/16227 , H01L2224/48227 , H01L2224/81191 , H01L2924/00014 , H01L2924/15159 , H05K1/028 , H05K1/189 , H05K2201/09227 , H05K2201/09272 , H05K2201/09281 , H05K2201/10674 , H01L2224/45099
Abstract: A chip on film package includes a base substrate, an input line, an integrated circuit (IC) chip and an output line. The input line is disposed on the base substrate. The IC chip is electrically connected to the input line. The output line includes a main output and a sub output line. The main output line is electrically connected to the IC chip and extends in a first direction from the IC chip. The sub output line is electrically connected to the IC chip. The sub output line includes at least six bending parts, and is extended in the first direction.
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公开(公告)号：US20170215275A1
公开(公告)日：2017-07-27
申请号：US15388600
申请日：2016-12-22
Applicant: ALPINE ELECTRONICS, INC.
Inventor： Kenji Iidaka
CPC classification number: H05K1/0228 , H05K1/115 , H05K1/116 , H05K1/181 , H05K2201/0245 , H05K2201/09236 , H05K2201/09263 , H05K2201/09272
Abstract: A wiring structure includes a plurality of wiring patterns. An interval between the adjacent wiring patterns is shortened in the parallel wiring portions. In wiring path change portions, the wiring patterns are extended at a slope with respect to an X direction, and an interval between the adjacent wiring patterns is more widened than the interval. A crosstalk noise can be reduced by widening the interval between the wiring patterns using the wiring path change portions without making an area occupied by a wiring region extremely increased.
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公开(公告)号：US09717141B1
公开(公告)日：2017-07-25
申请号：US14108724
申请日：2013-12-17
Inventor： Troy T. Tegg
CPC classification number: H05K1/0268 , A61B8/12 , A61B8/445 , H05K1/118 , H05K2201/056 , H05K2201/09272 , H05K2201/09709 , H05K2201/10189
Abstract: A flexible printed circuit which includes a flexible substrate, a plurality of conductive pads, and a plurality of conductive traces that conductively connect to at least two conductive pads. The plurality of conductive pads and traces are defined on the flexible substrate. The flexible substrate has a first portion and a second portion. The first portion has at least two sets of conductive pads. The second portion has at least one set of conductive pads and is configured to conductively connect to a testing device. After the flexible printed circuit is tested, the second portion of the flexible substrate is detached from the first portion of the flexible substrate.
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公开(公告)号：US09664964B2
公开(公告)日：2017-05-30
申请号：US14678406
申请日：2015-04-03
Applicant: SAMSUNG DISPLAY CO., LTD.
Inventor： Chong-Guk Lee , Joo-Yeon Won , Se-Hui Jang , Su-Mi Moon , Dong-Wook Lee
IPC: H01L23/48 , G02F1/1345 , H01L27/12 , H01L23/498 , H05K1/02 , H01L23/00 , H05K1/18
CPC classification number: G02F1/13452 , H01L23/4985 , H01L24/16 , H01L24/48 , H01L27/124 , H01L2224/16227 , H01L2224/48227 , H01L2224/81191 , H01L2924/00014 , H01L2924/15159 , H05K1/028 , H05K1/189 , H05K2201/09227 , H05K2201/09272 , H05K2201/09281 , H05K2201/10674 , H01L2224/45099
Abstract: A chip on film package includes a base substrate, an input line, an integrated circuit (IC) chip and an output line. The input line is disposed on the base substrate. The IC Chip is electrically connected to the input line. The output line includes a main output and a sub output line. The main output line is electrically connected to the IC chip and extends in a first direction from the IC chip. The sub output line is electrically connected to the IC chip. The sub output line includes at least six bending parts, and is extended in the first direction.
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公开(公告)号：US09648739B2
公开(公告)日：2017-05-09
申请号：US14558614
申请日：2014-12-02
Applicant: CANON KABUSHIKI KAISHA
Inventor： Takashi Aoki , Yasuhiro Sawada
CPC classification number: H05K1/111 , H05K1/0243 , H05K3/3442 , H05K2201/09272 , H05K2201/09427 , H05K2201/09727 , H05K2201/0979 , H05K2201/10015 , H05K2201/10636 , H05K2201/10651 , Y02P70/611
Abstract: An electronic component mounting structure includes a first land, a second land making a pair with the first land, an electronic component having a chip shape and including a first electrode connected to the first land and a second electrode connected to the second land, a first wiring pattern connected to the first land, and a second wiring pattern connected to the second land and including a first partial pattern overlapping a portion of a body of the electronic component in planar view, the portion being not covered with the pair of electrodes, a second partial pattern formed integral with the first partial pattern and overlapping the first electrode of the electronic component in planar view, and a third partial pattern formed integral with the second partial pattern and parallel to the first wiring pattern.
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