公开(公告)号：US07667480B2

公开(公告)日：2010-02-23

申请号：US12093232

申请日：2006-11-08

Applicant: Yasuhiro Okuda ,  Akihisa Hosoe ,  Taro Fujita

Inventor： Yasuhiro Okuda ,  Akihisa Hosoe ,  Taro Fujita

IPC: G01R31/02

CPC classification number: H01R13/03 ,  H01R4/04 ,  H01R11/01 ,  H01R43/0235 ,  H01R43/0249 ,  H01R43/0256 ,  H05K3/0035 ,  H05K3/326 ,  H05K2201/0116 ,  H05K2201/015 ,  H05K2201/0394 ,  H05K2201/09509 ,  H05K2201/09527 ,  H05K2201/10378 ,  H05K2201/10674 ,  H05K2203/0156 ,  Y10T29/49204

Abstract: Provided is an anisotropic conductive sheet (8) having heat resistance and cold resistance and suitable for connection of electrodes. The anisotropic conductive sheet of the present invention has conductivity in the thickness direction, wherein the base film (1), which is a film made of synthetic resin having an electrical insulation property, has a plurality of holes (3) formed in the thickness direction, and the holes (3) are open to one main surface of the base film and closed to the other main surface, wherein a metal is adhered to the closed parts (2a) and the inner walls (2b) of the holes (3) so that by contacting electrodes (7) with the closed parts (2a) respectively from the outside, the electrodes (7) can electrically be connected through the adhered metal to the main surface where the holes (3) are open.

Abstract translation: 提供具有耐热性和耐寒性并适合于连接电极的各向异性导电片（8）。 本发明的各向异性导电片在厚度方向上具有导电性，其中，作为由具有电绝缘性的合成树脂制成的膜的基膜（1）具有沿厚度方向形成的多个孔（3） 并且孔（3）对基膜的一个主表面开放并且与另一个主表面闭合，其中金属粘附到孔（3）的封闭部分（2a）和内壁（2b） 使得通过从外部分别将电极（7）与闭合部分（2a）接触，电极（7）可以通过粘附的金属电连接到孔（3）打开的主表面。

公开(公告)号：US20100032196A1

公开(公告)日：2010-02-11

申请号：US12537391

申请日：2009-08-07

Applicant: Kentaro KANEKO ,  Kazuhiro Kobayashi ,  Yoshiki Okushima ,  Kotaro Kodani

Inventor： Kentaro KANEKO ,  Kazuhiro Kobayashi ,  Yoshiki Okushima ,  Kotaro Kodani

IPC: H05K1/16 ,  H05K1/11 ,  B32B37/00

CPC classification number: H05K1/113 ,  B32B37/02 ,  B32B2457/08 ,  H01L21/4846 ,  H01L21/563 ,  H01L21/6835 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L24/02 ,  H01L24/16 ,  H01L2221/68345 ,  H01L2224/0401 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H05K3/20 ,  H05K3/421 ,  H05K3/4644 ,  H05K3/4682 ,  H05K2201/037 ,  H05K2201/09527 ,  H05K2201/0979 ,  H05K2201/09981 ,  Y10T156/10 ,  H01L2924/00012 ,  H01L2924/00

Abstract: In a multilayer wiring board having a wiring layer, a pad, an insulating layer provided between the wiring layer and the pad, and a plurality of connecting vias provided on the insulating layer and connecting the wiring layer to the pad, the connecting vias are provided on a peripheral edge of the pad.

Abstract translation: 在具有布线层，焊盘，设置在布线层和焊盘之间的绝缘层以及设置在绝缘层上并将布线层连接到焊盘的多个连接通孔的多层布线板中，提供连接通孔 在垫的外围边缘。

公开(公告)号：US20090223046A1

公开(公告)日：2009-09-10

申请号：US12393478

申请日：2009-02-26

Applicant: Kei Murayama ,  Mitsutoshi Higashi ,  Masahiro Sunohara

Inventor： Kei Murayama ,  Mitsutoshi Higashi ,  Masahiro Sunohara

IPC: H05K3/02

CPC classification number: H05K3/3473 ,  H01L21/4857 ,  H01L21/568 ,  H01L21/6835 ,  H01L24/16 ,  H01L24/81 ,  H01L24/97 ,  H01L2221/68345 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/351 ,  H05K1/113 ,  H05K3/005 ,  H05K3/007 ,  H05K3/4682 ,  H05K2201/0367 ,  H05K2201/068 ,  H05K2201/09527 ,  H05K2201/10674 ,  H05K2203/0108 ,  H05K2203/0113 ,  H05K2203/016 ,  H05K2203/0338 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A method of manufacturing a wiring board having a semiconductor chip mounting surface for mounting a semiconductor chip thereon which is manufactured by a process including a step of forming a wiring layer and an insulating layer on a support board and a step of removing the support board, including a peeling layer forming step of forming a peeling layer on the support board formed by a material having a coefficient of thermal expansion which is equal to that of a semiconductor substrate constituting the semiconductor chip, and a support board removing step of removing the support board by carrying out a predetermined treatment over the peeling layer.

Abstract translation: 一种制造具有用于安装半导体芯片的半导体芯片安装表面的布线板的方法，其通过包括在支撑板上形成布线层和绝缘层的步骤的工艺制造，以及去除支撑板的步骤， 包括在由具有与构成半导体芯片的半导体衬底的热膨胀系数相同的热膨胀系数的材料形成的支撑板上形成剥离层的剥离层形成步骤，以及去除支撑板的支撑板移除步骤 通过对剥离层进行预定处理。

公开(公告)号：US20090019693A1

公开(公告)日：2009-01-22

申请号：US12237955

申请日：2008-09-25

Applicant: Masaru Takada ,  Hiroyuki Kobayashi ,  Kenji Chihara ,  Hisashi Minoura ,  Kiyotaka Tsukada ,  Mitsuhiro Kondo

Inventor： Masaru Takada ,  Hiroyuki Kobayashi ,  Kenji Chihara ,  Hisashi Minoura ,  Kiyotaka Tsukada ,  Mitsuhiro Kondo

IPC: H05K3/10

CPC classification number: H01L24/32 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/32057 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73265 ,  H01L2224/83385 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/112 ,  H05K1/116 ,  H05K3/0008 ,  H05K3/0035 ,  H05K3/027 ,  H05K3/242 ,  H05K3/243 ,  H05K3/28 ,  H05K3/3452 ,  H05K3/3457 ,  H05K3/4038 ,  H05K3/421 ,  H05K3/428 ,  H05K3/4602 ,  H05K3/4611 ,  H05K2201/0305 ,  H05K2201/0394 ,  H05K2201/09381 ,  H05K2201/09509 ,  H05K2201/09527 ,  H05K2201/0959 ,  H05K2201/09781 ,  H05K2203/0554 ,  H05K2203/0571 ,  H05K2203/107 ,  H05K2203/175 ,  Y10S428/901 ,  Y10T29/49117 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T428/24917 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2224/85399

Abstract: A solder resist comprising a thermosetting resin is printed on a surface of an insulating board (7) having a conductor circuit (6). The solder resist is then heat-cured to form an insulating film (1) having a low thermal expansion coefficient. A laser beam (2) is then applied to the portion of the insulating film in which an opening is to be formed, to burn off the same portion for forming an opening (10), whereby the conductor circuit (6) is exposed. This opening may be formed as a hole for conduction by forming a metal plating film on an inner surface thereof. It is preferable that an external connecting pad be formed so as to cover the opening. The film of coating of a metal is formed by using an electric plating lead, which is preferably cut off by a laser beam after the electric plating has finished.

Abstract translation: 在具有导体电路（6）的绝缘板（7）的表面上印刷包括热固性树脂的阻焊剂。 然后将阻焊剂热固化以形成具有低热膨胀系数的绝缘膜（1）。 然后将激光束（2）施加到要形成开口的绝缘膜的部分，以烧掉用于形成开口（10）的相同部分，由此导体电路（6）暴露。 该开口可以通过在其内表面上形成金属电镀膜而形成为导电孔。 优选地，形成外部连接垫以覆盖开口。 通过使用在电镀完成后优选用激光束切断的电镀铅来形成金属涂膜。

公开(公告)号：US07419382B2

公开(公告)日：2008-09-02

申请号：US11589332

申请日：2006-10-30

Applicant: Daigo Suzuki ,  Akihiko Happoya ,  Hidenori Tanaka

Inventor： Daigo Suzuki ,  Akihiko Happoya ,  Hidenori Tanaka

IPC: H01R12/00

CPC classification number: H01L24/11 ,  H01L24/742 ,  H01L24/81 ,  H01L2224/1131 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/16237 ,  H01L2224/81121 ,  H01L2224/81136 ,  H01L2224/81203 ,  H01L2224/81801 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H05K1/0269 ,  H05K1/112 ,  H05K1/186 ,  H05K3/303 ,  H05K3/4623 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/09527 ,  H05K2201/10674 ,  H05K2203/166

Abstract: According to one embodiment, a printed circuit board includes a first dielectric layer, a circuit component mounted on the first dielectric layer, and a second dielectric layer. The first dielectric layer is provided with a via hole which opens at a surface thereof and in which a conductive layer is provided, and a conductive pattern connected electrically to the conductive layer of the via hole. The circuit component is provided with a bump at least a part of which is inserted in the via hole and bonded to an inner surface of the via hole. The second dielectric layer is formed provided with another conductive pattern and laminated to the first dielectric layer to cover the circuit component.

Abstract translation: 根据一个实施例，印刷电路板包括第一电介质层，安装在第一电介质层上的电路部件和第二电介质层。 第一介电层设置有在其表面开口并且其中设置有导电层的通孔以及与通孔的导电层电连接的导电图案。 电路部件设置有凸块，其中至少一部分插入通孔中并结合到通孔的内表面。 第二电介质层被形成为设置有另一个导电图案并层压到第一电介质层以覆盖电路部件。

公开(公告)号：US20070263370A1

公开(公告)日：2007-11-15

申请号：US11555881

申请日：2006-11-02

Applicant: AYAO NIKI

Inventor： AYAO NIKI

IPC: H05K1/03

CPC classification number: H05K1/115 ,  H05K3/421 ,  H05K3/4644 ,  H05K2201/0352 ,  H05K2201/0394 ,  H05K2201/09527 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2203/0554 ,  Y10T29/49124 ,  Y10T29/49155 ,  Y10T29/49162

Abstract: A multilayer printed wiring board includes one or more resin layers having via-holes and a core layer having via-holes. The via-holes formed in the one or more resin layers are open in the direction opposite to the direction in which the via-holes formed in the core layer are open. A method for manufacturing a multilayer printed wiring board includes a step of preparing a single- or double-sided copper-clad laminate; a step of forming lands by processing the copper-clad laminate; a step of forming a resin layer on the upper surface of the copper-clad laminate, forming openings for via-holes in the resin layer, and then forming the via-holes; and a step of forming openings for via-holes in the lower surface of the copper-clad laminate and then forming the via-holes.

Abstract translation: 多层印刷线路板包括一个或多个具有通孔的树脂层和具有通孔的芯层。 在一个或多个树脂层中形成的通孔在与芯层中形成的通路孔打开的方向相反的方向上开口。 一种制造多层印刷线路板的方法包括制备单面或双面覆铜层压板的步骤; 通过加工覆铜层压板来形成焊盘的步骤; 在覆铜层压板的上表面上形成树脂层的步骤，在树脂层中形成通孔的开口，然后形成通孔; 以及在覆铜层压板的下表面中形成用于通孔的开口，然后形成通孔的步骤。

公开(公告)号：US20070193679A1

公开(公告)日：2007-08-23

申请号：US11567344

申请日：2006-12-06

Applicant: Yoshiyuki IWATA

Inventor： Yoshiyuki IWATA

IPC: B32B38/10 ,  B32B38/04 ,  B32B37/12

CPC classification number: B32B38/10 ,  B32B2310/0843 ,  B32B2457/08 ,  H05K1/115 ,  H05K3/20 ,  H05K3/4602 ,  H05K3/4682 ,  H05K2201/09527 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2203/0554 ,  H05K2203/1536 ,  Y10T29/49165 ,  Y10T156/1056 ,  Y10T156/1057

Abstract: The present invention intends to provide a novel printed wiring board manufacturing method by which printed wiring boards can be manufactured with efficiency. A method of manufacturing a printed wiring board (FIG. 1B) according to the present invention includes a step for preparing two sets of copper clad laminates (FIG. 2A), a step for bonding the copper clad laminates (FIG. 2B), steps for forming lands on both surfaces of a bonded laminate (FIGS. 2C to 2E), steps for forming respective resin layers on both surfaces of the bonded laminate and forming via hole openings to form respective via holes (FIGS. 2F to 2L), a step for forming a resin layer and forming a via hole opening to form a via hole (FIG. 2M), a step for separating the bonded laminate from each other (FIG. 2N) and steps for forming via hole openings from the bonded surface of the separated laminate to form via holes (FIGS. 20 to 2T). Via holes (33-1, 33-2) formed on the resin layer and a via hole (42) formed on the laminate are opened in the opposite directions.

Abstract translation: 本发明旨在提供一种能够有效地制造印刷电路板的新颖的印刷线路板制造方法。 根据本发明的制造印刷电路板（图1B）的方法包括制备两组铜包覆层压板的步骤（图2A），用于粘合覆铜层压板的步骤（图2B ），用于在接合层压体的两个表面上形成焊盘的步骤（图2C-2E），在接合层叠体的两个表面上形成各个树脂层并形成通孔开口以形成相应的通孔的步骤（图2 F-2L），用于形成树脂层并形成通孔开口以形成通孔的步骤（图2M），分离粘合层压体的步骤（图2N）和步骤 从分离的层压体的接合表面形成通孔开口以形成通孔（图20至图2T）。 形成在树脂层上的通孔（33-1,33-2）和形成在层叠体上的通孔（42）沿相反方向打开。

公开(公告)号：US20060157272A1

公开(公告)日：2006-07-20

申请号：US11384744

申请日：2006-03-20

Applicant: Christopher Jones

Inventor： Christopher Jones

IPC: H05K1/11

CPC classification number: H05K3/421 ,  H01L23/49827 ,  H01L2224/16 ,  H01L2924/15311 ,  H05K1/115 ,  H05K3/243 ,  H05K3/4602 ,  H05K2201/0367 ,  H05K2201/09509 ,  H05K2201/09527 ,  H05K2203/0574 ,  H05K2203/0733 ,  H05K2203/1476 ,  Y10T29/49165

Abstract: A system may include a first microvia pad, a second microvia pad having a projection extending in a direction toward the first microvia pad, and a microvia electrically coupled to the first microvia pad and to the second microvia pad.

Abstract translation: 系统可以包括第一微孔垫，具有沿朝向第一微孔垫的方向延伸的突起的第二微孔垫，以及电耦合到第一微孔垫和第二微孔垫的微孔。

公开(公告)号：US20050205516A1

公开(公告)日：2005-09-22

申请号：US11073615

申请日：2005-03-08

Applicant: Hiroshi Sugimoto ,  Tatsuya Ohtaka ,  Shigeharu Takahagi

Inventor： Hiroshi Sugimoto ,  Tatsuya Ohtaka ,  Shigeharu Takahagi

IPC: B23K26/00 ,  B23K26/38 ,  B23K101/42 ,  H01L23/12 ,  H01L23/498 ,  H01L23/50 ,  H05K1/02 ,  H05K1/11 ,  H05K3/00 ,  H05K3/06 ,  H05K3/46 ,  H01B13/00

CPC classification number: H01L23/50 ,  H01L23/49822 ,  H01L23/49838 ,  H01L2224/05026 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/3011 ,  H05K1/0237 ,  H05K1/114 ,  H05K3/0035 ,  H05K3/4652 ,  H05K2201/0394 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/09527 ,  H01L2224/05599

Abstract: A wiring board with microstrip structure has: a first conductor layer that is provided with conductor wirings to be connected to a semiconductor chip in its external terminal (bonding pad); a second conductor layer that is provided with a conductor pattern connected through a via to a ground wiring, for supplying a power supply of ground potential to the semiconductor chip; and a third conductor layer that is provided with a power supply terminal connected through a via to a power supply wiring for supplying an operation power supply of a potential other than the ground potential to the semiconductor chip, a signal terminal connected through a via to a signal wiring for transmitting an electric signal, and a ground terminal connected through a via to the conductor pattern in the second conductor layer.

Abstract translation: 具有微带结构的布线板具有：第一导体层，其在其外部端子（接合焊盘）中设置有与半导体芯片连接的导体布线; 第二导体层，其设置有通过通孔连接到接地布线的导体图案，用于向半导体芯片提供接地电位; 以及第三导体层，其具有通过通孔连接到电源布线的电源端子，用于向半导体芯片提供除了地电位以外的电位的操作电源，通过通孔连接到 用于发送电信号的信号线路，以及通过通孔连接到第二导体层中的导体图案的接地端子。

公开(公告)号：US06931724B2

公开(公告)日：2005-08-23

申请号：US10207259

申请日：2002-07-30

Applicant: Akio Rokugawa ,  Masayuki Sasaki ,  Yuichi Matsuda

Inventor： Akio Rokugawa ,  Masayuki Sasaki ,  Yuichi Matsuda

IPC: H01L23/12 ,  H01L23/498 ,  H05K1/11 ,  H05K3/00 ,  H05K3/04 ,  H05K3/10 ,  H05K3/20 ,  H05K3/38 ,  H05K3/46 ,  H01K3/10

CPC classification number: H05K3/4682 ,  H01L21/6835 ,  H01L23/49811 ,  H01L23/49822 ,  H01L2221/68345 ,  H01L2224/16225 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/3025 ,  H05K1/113 ,  H05K3/007 ,  H05K3/045 ,  H05K3/108 ,  H05K3/20 ,  H05K3/205 ,  H05K3/388 ,  H05K2201/09509 ,  H05K2201/09527 ,  H05K2201/09563 ,  H05K2203/0152 ,  H05K2203/0376 ,  H05K2203/0384 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T29/49345

Abstract: A method of producing a multilayered substrate having: a first face being provided with pads bondable to electrode terminals of a semiconductor element, and a body containing a plurality of wiring line layers and insulation layers successively formed from the side of the multilayered substrate at which the face for mounting a semiconductor element is located, wherein the final insulating layer forms provides a second face of the multilayered substrate. The successive wiring line layers are connected by vias, and the second face has external connection terminal pads. The pads on the first face are formed on a metal sheet, a first layer of insulating material is formed on the metal sheet so as to cover the pads formed thereon, holes are formed through the insulating material to expose the end face of the pad, and a patterned metal layer is formed to provide a layer of wiring lines and vias connecting the pads with the wiring line on the layer of insulating material. Subsequently, layers of insulation material are formed to cover the layers of wiring lines, where vias are formed in the insulating material layers, and then patterned metal wiring line layers and filled vias are formed, until the predetermined number of sets of an insulation layer and a wiring line layer is obtained. The metal sheet is then removed.

Abstract translation: 一种多层基板的制造方法，其特征在于，具有：第一面，其具有可与半导体元件的电极端子连接的焊盘;以及主体，其包含从所述多层基板的一侧依次形成的多个布线层和绝缘层， 定位用于安装半导体元件的面，其中最终绝缘层形成提供多层基底的第二面。 连续的布线层通过通孔连接，第二面具有外部连接端子焊盘。 第一面上的焊盘形成在金属板上，在金属板上形成第一绝缘材料层，以覆盖形成在其上的焊盘，通过绝缘材料形成孔，露出焊盘的端面， 并且形成图案化金属层以提供将焊盘与绝缘材料层上的布线连接的布线线和通孔层。 随后，形成绝缘材料层以覆盖在绝缘材料层中形成通孔的布线层，然后形成图案化的金属布线层和填充的通孔，直到预定数量的绝缘层和 得到布线层。 然后去除金属片。