公开(公告)号：US20100187000A1

公开(公告)日：2010-07-29

申请号：US12594183

申请日：2008-02-07

Applicant: Juergen Egerter ,  Walter Roethlingshoefer ,  Markus Werner

Inventor： Juergen Egerter ,  Walter Roethlingshoefer ,  Markus Werner

IPC: H05K1/02 ,  H05K3/14 ,  H05K3/46

CPC classification number: H01L21/4807 ,  H01L21/4857 ,  H05K1/0306 ,  H05K3/465 ,  H05K3/4667 ,  H05K2201/09881 ,  H05K2203/0169 ,  H05K2203/1344 ,  H05K2203/1366 ,  Y10T29/49126 ,  Y10T29/4916 ,  Y10T29/49163

Abstract: A method for producing a ceramic multilayer circuit system, and a corresponding multilayer circuit system are provided. An embodiment of the method includes sequential deposition of a plurality of circuit layers of the multilayer circuit system on a substrate using a powder spray method; pressing of the deposited plurality of circuit layers; and thermal sintering of the pressed plurality of circuit layers. The individual circuit layers have electrically conductive areas made of at least one conductive material and electrically insulating areas made of at least one ceramic material.

Abstract translation: 提供一种陶瓷多层电路系统的制造方法以及相应的多层电路系统。 该方法的实施例包括使用粉末喷涂方法将多层电路系统的多个电路层顺次沉积在基板上; 压制沉积的多个电路层; 和压制的多个电路层的热烧结。 单个电路层具有由至少一种导电材料制成的导电区域和由至少一种陶瓷材料制成的电绝缘区域。

公开(公告)号：US07754978B2

公开(公告)日：2010-07-13

申请号：US11397802

申请日：2006-04-05

Applicant: Takashi Kariya ,  Toshiki Furutani

Inventor： Takashi Kariya ,  Toshiki Furutani

IPC: H01R12/04 ,  H05K1/11

CPC classification number: H01L24/16 ,  H01L21/4857 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/73253 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01057 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/30105 ,  H05K1/0271 ,  H05K1/0373 ,  H05K1/111 ,  H05K1/115 ,  H05K3/243 ,  H05K3/28 ,  H05K3/4007 ,  H05K3/4602 ,  H05K2201/0133 ,  H05K2201/0367 ,  H05K2201/068 ,  H05K2201/09881 ,  H05K2201/10674 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49204 ,  H01L2924/00 ,  H01L2224/0401

Abstract: A multilayer printed wiring board 10 includes: a core substrate 20; a build-up layer 30 formed on the core substrate 20 and having a conductor pattern 32 on an upper surface; a low elastic modulus layer 40 formed on the build-up layer 30; lands 52 that are disposed on an upper surface of the low elastic modulus layer 40 and connected via solder bumps 66 to a semiconductor chip 70; and conductor posts 50 that are passing through the low elastic modulus layer 40 and electrically connecting lands 52 with conductor patterns 32. The conductor posts 50 are formed to have the diameters of an upper portion and a lower portion of 80 μm, the diameter of an intermediate portion of 35 μm, the height of 200 μm, and the aspect ratio Rasp (height/minimum diameter) of 5.7 and the maximum diameter/minimum diameter of 2.3.

Abstract translation: 多层印刷线路板10包括：芯基板20; 形成在芯基板20上并且在上表面上具有导体图案32的堆积层30; 形成在积层30上的低弹性模量层40; 焊盘52设置在低弹性模量层40的上表面上并通过焊锡凸块66连接到半导体芯片70; 以及导体柱50，其穿过低弹性模量层40和电连接焊盘52与导体图案32.导体柱50形成为具有80μm的上部和下部的直径， 中间部分为35μm，高度为200μm，纵横比Rasp（高/最小直径）为5.7，最大直径/最小直径为2.3。

公开(公告)号：US20100122840A1

公开(公告)日：2010-05-20

申请号：US12694322

申请日：2010-01-27

Applicant: Motoo ASAI ,  Dongdong Wang ,  Takahiro Mori

Inventor： Motoo ASAI ,  Dongdong Wang ,  Takahiro Mori

IPC: H05K1/02 ,  H05K1/03

CPC classification number: H05K3/423 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15312 ,  H05K1/036 ,  H05K3/0032 ,  H05K3/0035 ,  H05K3/0038 ,  H05K3/108 ,  H05K3/181 ,  H05K3/381 ,  H05K3/385 ,  H05K3/387 ,  H05K3/388 ,  H05K3/426 ,  H05K3/427 ,  H05K3/4602 ,  H05K2201/0195 ,  H05K2201/0352 ,  H05K2201/0355 ,  H05K2201/0394 ,  H05K2201/09536 ,  H05K2201/09563 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/09736 ,  H05K2201/09881 ,  H05K2203/0315 ,  H05K2203/0733 ,  H05K2203/0773 ,  H05K2203/1476 ,  Y10T29/49126 ,  Y10T29/49144 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2224/05599

Abstract: A multi-layer printed circuit board including a core structure including resin layers and conductor circuits sandwiched by the resin layers, the core structure having a first surface and a second surface on an opposite side of the first surface, a first conductor layer including conductor circuits formed on the first surface of the core structure, and a second conductor layer including conductor circuits formed on the second surface of the core structure. The core structure includes a first via hole and a second via hole, the first via hole and the second via hole sandwich one or more conductor circuits in the core substrate and are positioned vertically to form a through hole electrically connecting respective ones of the conductor circuits of the first and the second conductor layers, and the first via hole and the second via hole are deviated from each other in a vertical direction.

Abstract translation: 一种多层印刷电路板，包括由树脂层和由树脂层夹在的导体电路的芯结构，芯结构具有在第一表面的相对侧的第一表面和第二表面，第一导体层包括导体电路 形成在芯结构的第一表面上，以及第二导体层，包括形成在芯结构的第二表面上的导体电路。 芯结构包括第一通孔和第二通孔，第一通孔和第二通孔夹着芯基板中的一个或多个导体电路并垂直定位，以形成电连接各个导体电路的通孔 的第一和第二导体层，并且第一通孔和第二通孔在垂直方向上彼此偏离。

公开(公告)号：US20100108637A1

公开(公告)日：2010-05-06

申请号：US12652255

申请日：2010-01-05

Applicant: Takashi KARIYA ,  Toshiki Furutani

Inventor： Takashi KARIYA ,  Toshiki Furutani

IPC: H01B13/00

CPC classification number: H01L24/16 ,  H01L21/4857 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/73253 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01057 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/30105 ,  H05K1/0271 ,  H05K1/0373 ,  H05K1/111 ,  H05K1/115 ,  H05K3/243 ,  H05K3/28 ,  H05K3/4007 ,  H05K3/4602 ,  H05K2201/0133 ,  H05K2201/0367 ,  H05K2201/068 ,  H05K2201/09881 ,  H05K2201/10674 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49204 ,  H01L2924/00 ,  H01L2224/0401

Abstract: A multilayer printed wiring board manufacturing method including forming conductor posts, which are of substantially uniform thickness and with which the top surfaces are protected by a resist, on a conductor pattern disposed on an upper surface of a build-up layer formed on a core substrate, shaping the conductor posts to have a constriction by adjusting the time of immersion in an etching solution that etches the conductor posts, forming a low elastic modulus layer of substantially the same height as the conductor posts after removing the resist at the top surfaces, and forming mounting electrodes on upper surfaces of the conductor posts.

Abstract translation: 一种多层印刷线路板制造方法，包括形成基本上均匀的厚度并且顶表面被抗蚀剂保护的导体柱布置在形成在芯基板上的积聚层的上表面上的导体图案上 通过调节蚀刻导体柱的蚀刻溶液中的浸渍时间来形成导体柱以形成收缩，在去除顶表面上的抗蚀剂之后形成与导体柱基本上相同的高度的低弹性模量层，以及 在导体柱的上表面上形成安装电极。

公开(公告)号：US07657999B2

公开(公告)日：2010-02-09

申请号：US11868640

申请日：2007-10-08

Applicant: Thomas Peter Brody

Inventor： Thomas Peter Brody

IPC: H05K3/10

CPC classification number: H05K3/28 ,  H05K3/143 ,  H05K3/4647 ,  H05K3/467 ,  H05K2201/09881 ,  H05K2203/025 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49155

Abstract: In a method of forming an electrical circuit assembly, a substrate is provided including a plurality of first segments that form an electrical circuit. The first segments have surfaces that rise above surfaces of other segments that form the electrical circuit. All of the segments are deposited on the substrate via one or more shadow mask vapor deposition processes in a vacuum. A photoresist caused to cover all of the segments is hardened and then abraded until surfaces of the first segments are exposed, but surfaces of the other segments are not exposed, and a surface of the abraded photoresist is at the same level as the exposed surfaces of the first segments. Second segments can be deposited on the exposed surfaces of the first segments via a shadow mask vapor deposition process in a vacuum to a level above the top surface of the abraded photoresist.

Abstract translation: 在形成电路组件的方法中，提供了包括形成电路的多个第一段的衬底。 第一段具有在形成电路的其他段的表面上方的表面。 所有的片段通过真空中的一个或多个荫罩气相沉积工艺沉积在衬底上。 导致覆盖所有片段的光致抗蚀剂被硬化，然后磨损直到第一片段的表面露出，但是其它片段的表面不被暴露，并且磨损的光致抗蚀剂的表面处于与暴露的表面相同的水平 第一段。 第二段可以通过在真空中的荫罩气相沉积工艺在第一段的暴露表面上沉积到磨损光致抗蚀剂的顶表面上方的水平。

公开(公告)号：US20090280617A1

公开(公告)日：2009-11-12

申请号：US12358852

申请日：2009-01-23

Applicant: Shih-Lian Cheng

Inventor： Shih-Lian Cheng

IPC: H01L21/71

CPC classification number: H05K1/165 ,  H05K1/092 ,  H05K1/167 ,  H05K1/183 ,  H05K3/427 ,  H05K3/4602 ,  H05K3/4623 ,  H05K3/4652 ,  H05K2201/086 ,  H05K2201/09736 ,  H05K2201/09881 ,  H05K2203/1147 ,  H05K2203/1453

Abstract: A fabricating process for a substrate with an embedded passive component is provided. The fabricating process includes the following steps. First, a substrate including a top conductive layer, a bottom conductive layer, and at least a dielectric layer is provided. The top conductive layer and the bottom conductive layer are separately disposed on a top surface and a bottom surface of the dielectric layer. Next, a plurality of plating through holes is formed in the substrate. Then, the top and the bottom conductive layers are patterned to form a patterned top conductive layer and a patterned bottom conductive layer separately, and the dielectric layer is exposed in part. The patterned top conductive layer and the patterned bottom conductive layer have many traces and many trenches formed by the traces. Thereafter, the trenches are filled with a material, wherein the traces and the material are adapted for forming the passive component.

Abstract translation: 提供了一种具有嵌入式无源元件的基板的制造工艺。 制造过程包括以下步骤。 首先，提供包括顶部导电层，底部导电层和至少介电层的基板。 顶导电层和底导电层分别设置在电介质层的顶表面和底表面上。 接下来，在基板上形成多个电镀通孔。 然后，对顶部和底部导电层进行图案化以分别形成图案化的顶部导电层和图案化的底部导电层，并且介电层部分暴露。 图案化的顶部导电层和图案化的底部导电层具有许多迹线和由迹线形成的许多沟槽。 此后，沟槽填充有材料，其中迹线和材料适于形成无源部件。

公开(公告)号：US07604858B2

公开(公告)日：2009-10-20

申请号：US11200184

申请日：2005-08-10

Applicant: Kyotaro Abe ,  Tamotsu Ishiyama ,  Shigeki Sato

Inventor： Kyotaro Abe ,  Tamotsu Ishiyama ,  Shigeki Sato

IPC: C08B29/00 ,  B05D5/00 ,  B05D3/02 ,  B32B18/00

CPC classification number: C04B35/6342 ,  C04B35/4682 ,  C04B35/6261 ,  C04B35/62625 ,  C04B35/6263 ,  C04B35/6264 ,  C04B35/62665 ,  C04B35/632 ,  C04B35/64 ,  C04B2235/3206 ,  C04B2235/3215 ,  C04B2235/3225 ,  C04B2235/3239 ,  C04B2235/3262 ,  C04B2235/3436 ,  C04B2235/3454 ,  C04B2235/5445 ,  C04B2235/6025 ,  C04B2235/6582 ,  C04B2235/663 ,  H01G4/308 ,  H05K1/0306 ,  H05K3/207 ,  H05K3/4611 ,  H05K3/4629 ,  H05K2201/09881 ,  H05K2203/0156 ,  Y10T428/252

Abstract: A release layer paste used for producing a multilayer electronic device, used in combination with an electrode layer paste including terpineol, dehydroterpineol, terpineol acetate, or dehydroterpineol acetate and including a ceramic powder, organic vehicle, plasticizer, and dispersion agent, the organic vehicle containing a binder having polyvinyl acetal as its main ingredient, a ratio (P/B) of the ceramic powder and the binder and plasticizer being controlled to 1.33 to 5.56 (however, excluding 5.56).

Abstract translation: 与包含萜品醇，脱氢萜品醇，萜品醇乙酸酯或脱氢萜品醇乙酸酯的电极层糊剂组合使用的包含陶瓷粉末，有机载体，增塑剂和分散剂的多层电子器件的剥离层糊剂，含有 以聚乙烯醇缩醛为主要成分的粘合剂，将陶瓷粉末和粘合剂与增塑剂的比例（P / B）控制在1.33至5.56（但不包括5.56）。

公开(公告)号：US20090258194A1

公开(公告)日：2009-10-15

申请号：US12101449

申请日：2008-04-11

Applicant: John Richard Dangler ,  Matthew Stephen Doyle

Inventor： John Richard Dangler ,  Matthew Stephen Doyle

IPC: B32B3/00 ,  B29C65/00

CPC classification number: H05K1/024 ,  H05K3/4652 ,  H05K2201/0195 ,  H05K2201/0715 ,  H05K2201/09236 ,  H05K2201/09881 ,  Y10T156/10 ,  Y10T428/24628

Abstract: Impedance control, and the uniformity of electrical and mechanical characteristics in electronic packaging are becoming more important as chip and bus speeds increase and manufacturing processes evolve. Current state of the art design and manufacture processes inherently introduce physical dielectric thickness variations into PCB cross sections. These thickness variations between the ground reference plane(s) and the signal layer(s) inject undesirable characteristic impedance variations and undesirable mechanical variations in thickness and surface topology. Therefore a multilayer electronic structure and a method of manufacture is presented.

Abstract translation: 阻抗控制以及电子封装中电气和机械特性的均匀性越来越重要，因为芯片和总线速度的增加和制造过程的演变。 当前的现有技术设计和制造工艺本身将物理电介质厚度变化引入PCB横截面。 接地参考平面与信号层之间的这些厚度变化引起了不需要的特性阻抗变化和厚度和表面拓扑结构中不期望的机械变化。 因此，提出了一种多层电子结构和制造方法。

公开(公告)号：US20090255715A1

公开(公告)日：2009-10-15

申请号：US12101441

申请日：2008-04-11

Applicant: John Richard Dangler ,  Matthew Stephen Doyle

Inventor： John Richard Dangler ,  Matthew Stephen Doyle

IPC: H05K1/02 ,  H05K3/46

CPC classification number: H05K1/024 ,  H01P11/003 ,  H05K1/0298 ,  H05K2201/0191 ,  H05K2201/0715 ,  H05K2201/09881 ,  H05K2203/063

Abstract: Impedance control, and the uniformity of electrical and mechanical characteristics in electronic packaging are becoming more important as chip and bus speeds increase and manufacturing processes evolve. Current state of the art design and manufacture processes inherently introduce physical dielectric thickness variations into multilayer cross sections. These thickness variations between the ground reference plane(s) and the signal layer(s) inject undesirable characteristic impedance variations and undesirable mechanical variations in thickness and surface topology. Therefore a multilayer structure and a method of manufacture are presented.

Abstract translation: 阻抗控制以及电子封装中电气和机械特性的均匀性越来越重要，因为芯片和总线速度的增加和制造过程的演变。 现有技术的设计和制造工艺现在将物理电介质厚度变化引入到多层横截面中。 接地参考平面与信号层之间的这些厚度变化引起了不需要的特性阻抗变化和厚度和表面拓扑结构中不期望的机械变化。 因此，提出了多层结构和制造方法。

公开(公告)号：US07592704B2

公开(公告)日：2009-09-22

申请号：US12169542

申请日：2008-07-08

Applicant: Terry L. Sterrett ,  Devendra Natekar

Inventor： Terry L. Sterrett ,  Devendra Natekar

IPC: H01L23/053 ,  H01L23/48

CPC classification number: H05K3/4038 ,  H01L21/486 ,  H01L23/49827 ,  H01L24/48 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/14 ,  H05K3/06 ,  H05K2201/09881 ,  H05K2201/10378 ,  H05K2201/2018 ,  H05K2203/0369 ,  H05K2203/1476 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: In one embodiment, a package-to-package stack is assembled comprising a first integrated circuit package, and a second integrated circuit package which are mechanically and electrically connected using an interposer. In one embodiment, the interposer 106 includes columnar interconnects which may be fabricated by etching a conductive member such as copper foil, for example. In one application, the pitch or center to center spacing of the columnar interconnects may be defined by masking techniques to provide an interconnect pitch suitable for a particular application. In yet another aspect, etching rates may be controlled to provide height to width aspect ratios of the columnar interconnects which are suitable for various applications.

Abstract translation: 在一个实施例中，组装包装堆叠包括第一集成电路封装和第二集成电路封装，其使用中介层机械和电连接。 在一个实施例中，插入器106包括可以通过例如蚀刻诸如铜箔的导电构件来制造的柱状互连。 在一个应用中，柱状互连的间距或中心到中心间隔可以通过掩模技术来定义，以提供适合于特定应用的互连间距。 在另一方面，可以控制蚀刻速率以提供适合于各种应用的柱状互连的高宽比长宽比。