公开(公告)号：US07232315B2

公开(公告)日：2007-06-19

申请号：US10554744

申请日：2004-04-23

Applicant: Shinji Uchida ,  Junya Kajimoto ,  Akihito Funakoshi

Inventor： Shinji Uchida ,  Junya Kajimoto ,  Akihito Funakoshi

IPC: H01R12/00

CPC classification number: H01R12/721 ,  H01R12/774 ,  H01R12/79 ,  H05K3/365 ,  H05K2201/0367 ,  H05K2201/09163 ,  H05K2201/09481

Abstract: A connection structure for a printed wiring board which enables high density integration is provided. A FCP 2 includes an exposed conductor part 2A including an insulating substrate 22 and a reinforcing plate 24 stacked with this substrate 22 via an elastic member 23. In the exposed conductor part 2A, conductors 21 each having a protrusion 20 formed on a surface is placed on the insulating substrate. The exposed conductor part 2A can be elastically deformed in the thickness direction in which the substrate 22, the reinforcing plate 24 and the like are stacked. A printed wiring board 1 is constructed by stacking an inner layer board 10 and a first outer layer board 11 and a second outer layer board 12 which sandwich this inner layer board 10. A notched groove 10A is formed on the inner layer board 10, and an insertion opening 10B is formed. Through-hole ports 11 which appear on the notched groove 10A side is placed on the first outer layer board. When the FPC 2 is inserted into the insertion opening 10B, the protrusion 20 of the FPC 2 fits with the through-hole port 11A from within insertion opening 10B and presses thereto.

Abstract translation: 提供了能够进行高密度集成的印刷电路板的连接结构。 FCP2包括通过弹性构件23包括绝缘基板22和与该基板22堆叠的加强板24的露出的导体部分2A。 在暴露的导体部分2A中，在绝缘基板上放置各自具有形成在表面上的突起20的导体21。 暴露的导体部分2A可以在层叠基板22，加强板24等的厚度方向上弹性变形。 印刷电路板1通过层叠内层板10和夹着该内层板10的第一外层板11和第二外层板12而构成。 在内层板10上形成切口槽10A，形成插入口10B。 出现在切口槽10A侧的通孔11被放置在第一外层板上。 当FPC2插入到插入口10B中时，FPC2的突起20从插入开口10B中的通孔端口11A配合并将其按压。

公开(公告)号：US20070126101A1

公开(公告)日：2007-06-07

申请号：US11633423

申请日：2006-12-05

Applicant: Ping-Yang Chuang

Inventor： Ping-Yang Chuang

IPC: H01L23/02

CPC classification number: H05K5/026 ,  H05K1/117 ,  H05K1/141 ,  H05K2201/09481 ,  H05K2201/10159

Abstract: A memory card module includes a first circuit board, and a second circuit board. On one surface of the first circuit board, there are flash memories and a controller. The second circuit board is installed at one end of the first circuit board and is electrically connected with the first circuit board so as to form a transmitting interface port. On a first surface of the second circuit board, there are a plurality of interface connecting points. On a second surface of the second circuit board, part of the second surface is hollowed out. A space formed between the hollowed out area and the corresponding first circuit board increases the area for circuit layouts and the mounting components for the first circuit board. Therefore, quantity of accommodated memory components may be increased so as to increase the total storage capacity of the memory card under limitation of small dimensions.

Abstract translation: 存储卡模块包括第一电路板和第二电路板。 在第一个电路板的一个表面上，有闪存和控制器。 第二电路板安装在第一电路板的一端并与第一电路板电连接以形成传输接口端口。 在第二电路板的第一表面上有多个界面连接点。 在第二电路板的第二表面上，第二表面的一部分被挖空。 在掏空区域和对应的第一电路板之间形成的空间增加了电路布局的面积和用于第一电路板的安装部件。 因此，可以增加容纳存储器部件的数量，以便在小尺寸的限制下增加存储卡的总存储容量。

公开(公告)号：US20070102830A1

公开(公告)日：2007-05-10

申请号：US11586209

申请日：2006-10-24

Applicant: Akira Muto ,  Tomokazu Tanaka

Inventor： Akira Muto ,  Tomokazu Tanaka

IPC: H01L23/52

CPC classification number: H05K1/118 ,  H01R12/79 ,  H05K1/0219 ,  H05K1/0237 ,  H05K3/42 ,  H05K2201/093 ,  H05K2201/09381 ,  H05K2201/09409 ,  H05K2201/09481 ,  H05K2201/09618 ,  H05K2201/09727 ,  Y10T29/4913 ,  Y10T29/49155

Abstract: A flexible printed circuit board has an insulation layer, a first signal wiring layer including a microstrip line, a second signal wiring layer including a signal connection terminal for allowing the microstrip line to connect the exterior connector electrically, and a ground conductive section having a ground connection terminal for connecting the exterior connector. The microstrip line and the signal connection terminal are connected to each other by a wiring via hole. The wiring via hole passes through the insulation layer, the first signal wiring layer, and the second signal wiring layer. The microstrip line has a taper section which gradually enlarges a width of the microstrip line toward the wiring via hole in the vicinity of the wiring via hole. The ground conductive section that corresponds to the microstrip line has a taper section with a shape matching the taper section of the microstrip line.

Abstract translation: 柔性印刷电路板具有绝缘层，包括微带线的第一信号布线层，包括用于允许微带线将外部连接器电连接的信号连接端子的第二信号布线层和具有地面的接地导电部分 用于连接外部连接器的连接端子。 微带线和信号连接端子通过布线孔相互连接。 布线通孔穿过绝缘层，第一信号布线层和第二信号布线层。 微带线具有锥形部，其在布线通孔附近逐渐扩大微带线的宽度朝向布线通孔。 对应于微带线的接地导电部分具有与微带线的锥形部分匹配的形状的锥形部分。

公开(公告)号：US20070090546A1

公开(公告)日：2007-04-26

申请号：US11338857

申请日：2006-01-25

Applicant: Takeshi Shioga ,  Yoshikatsu Ishizuki ,  Kanae Nakagawa ,  Taiji Sakai ,  Masataka Mizukoshi ,  John Baniecki ,  Kazuaki Kurihara

Inventor： Takeshi Shioga ,  Yoshikatsu Ishizuki ,  Kanae Nakagawa ,  Taiji Sakai ,  Masataka Mizukoshi ,  John Baniecki ,  Kazuaki Kurihara

IPC: H01L23/29

CPC classification number: H01L23/50 ,  H01L21/4846 ,  H01L21/4857 ,  H01L21/6835 ,  H01L23/49822 ,  H01L23/642 ,  H01L23/645 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K1/162 ,  H05K1/165 ,  H05K3/0023 ,  H05K3/0044 ,  H05K3/20 ,  H05K3/4614 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0317 ,  H05K2201/09481 ,  H05K2201/09509 ,  H05K2201/096 ,  H05K2201/09763 ,  H05K2201/10674 ,  H05K2203/016 ,  H05K2203/0733 ,  Y10T29/42 ,  Y10T29/435 ,  Y10T29/49002 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49156 ,  H01L2224/05599

Abstract: The interposer comprises a base 8 formed of a plurality of resin layers 68, 20, 32, 48; thin-film capacitors 18a, 18b buried between a first resin layer 68 of said plurality of resin layers and a second resin layer 20 of said plurality of resin layers, which include first capacitor electrodes 12a, 12b, second capacitor electrodes 16 opposed to the first capacitor electrode 12a, 12b and the second capacitor electrode 16, and a capacitor dielectric film 14 of a relative dielectric constant of 200 or above formed between the first capacitor electrode 12a, 12b and the second capacitor electrode 16; a first through-electrode 77a formed through the base 8 and electrically connected to the first capacitor electrode 12a, 12b; and a second through-electrode 77b formed through the base 8 and electrically connected to the second capacitor electrode 16.

Abstract translation: 插入件包括由多个树脂层68,20,32,48形成的基座8; 掩埋在所述多个树脂层的第一树脂层68和所述多个树脂层的第二树脂层20之间的薄膜电容器18a，18b，其包括第一电容器电极12a，12b，第二电容器电极16 与第一电容器电极12a，12b和第二电容器电极16相对，以及形成在第一电容器电极12a，12b和第二电容器电极16之间的相对介电常数为200或更大的电容器电介质膜14 ; 通过基座8形成并电连接到第一电容器电极12a，12b的第一贯通电极77a; 以及通过基底8形成并电连接到第二电容器电极16的第二贯通电极77b。

公开(公告)号：US20070023924A1

公开(公告)日：2007-02-01

申请号：US11516703

申请日：2006-09-07

Applicant: Tsukio Funaki

Inventor： Tsukio Funaki

IPC: H01L23/48

CPC classification number: H01L21/561 ,  H01L21/4853 ,  H01L21/563 ,  H01L21/6835 ,  H01L23/3114 ,  H01L24/11 ,  H01L24/13 ,  H01L24/97 ,  H01L2224/02333 ,  H01L2224/11 ,  H01L2224/11003 ,  H01L2224/1134 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81395 ,  H01L2224/97 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15184 ,  H01L2924/15311 ,  H01L2924/30107 ,  H01L2924/351 ,  H05K3/3457 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2201/0394 ,  H05K2201/09481 ,  H05K2203/0733 ,  H01L2224/81 ,  H01L2924/00

Abstract: Provided is a semiconductor device having a semiconductor chip mounted over a substrate, in which an interconnect is formed, by using an adhesive layer to permit contact conduction between a stud bump of the semiconductor chip and an interconnect of a tape substrate, wherein an adhesive layer formed integral as a film is adhered to each block made of substrates corresponding to a plurality of semiconductor devices and contact bonding under heat is conducted. The adhesive layer corresponding to the plurality of semiconductor devices is thus formed continuously and with this adhesive layer, the interconnect formation surface at the end portion of the substrate is covered. Moreover, with a thermosetting resin used as the adhesive layer, the semiconductor chip and substrate are adhered by contact bonding under heat while placing the substrate on a rigid heat insulating plate. According to the present invention, heat diffusion and deformation of the substrate upon contact bonding under heat can be prevented by the rigid heat insulating plate. Upon dicing, the peeling of the interconnect from the substrate can be prevented by holding the interconnect with the adhesive layer at the end portion of the substrate.

公开(公告)号：US20070020971A1

公开(公告)日：2007-01-25

申请号：US11479474

申请日：2006-06-30

Applicant: Keith Everett ,  Kevin Little ,  Jamie Anderson

Inventor： Keith Everett ,  Kevin Little ,  Jamie Anderson

IPC: H05K1/00

CPC classification number: H05K1/0218 ,  H05K3/325 ,  H05K9/0058 ,  H05K2201/09481 ,  H05K2201/09572 ,  H05K2201/09972 ,  H05K2201/10371

Abstract: A fibre optic module has a PCB with high frequency tracks. The PCB is housed within a housing having top and bottom parts, each having a series of metallized ridges. The PBC has through holes filled with solder. Thus, there is a series of electrical interconnections through the PBC, and the total length of any enclosed periphery is much shorter than the full periphery of the board so that high frequencies are attenuated.

Abstract translation: 光纤模块具有高频轨迹的PCB。 PCB被容纳在具有顶部和底部部分的壳体中，每个具有一系列金属化的脊。 PBC具有填充有焊料的通孔。 因此，通过PBC存在一系列电互连，并且任何封闭周边的总长度比板的整个周边短得多，使得高频衰减。

公开(公告)号：US07151050B2

公开(公告)日：2006-12-19

申请号：US11250110

申请日：2005-10-12

Applicant: Shih-Ping Hsu ,  Sao-Hsia Tang ,  Chao-Wen Shih ,  Ying-Tung Wang ,  Wen-Hung Hu

Inventor： Shih-Ping Hsu ,  Sao-Hsia Tang ,  Chao-Wen Shih ,  Ying-Tung Wang ,  Wen-Hung Hu

IPC: H01L21/44

CPC classification number: H05K3/243 ,  H05K3/108 ,  H05K3/3473 ,  H05K2201/0394 ,  H05K2201/09481 ,  H05K2201/09563 ,  H05K2203/0574 ,  H05K2203/0723

Abstract: A method for fabricating an electrical connection structure of a circuit board is proposed. A patterned resist layer is formed on the circuit board having a plurality of conductive pads, and a plurality of openings is formed in the resist layer to expose the conductive pads. A first conductive material and a second conductive material are successively deposited in the openings of the resist layer and on each of the conductive pads. Then, the resist layer is removed. Subsequently, a protective layer is applied on the circuit board and covers the first and second conductive materials formed on each of the conductive pads. Finally, the protective layer is thinned to expose the second conductive material corresponding in position to each of the conductive pads. Thus, the circuit board can be electrically connected to an external device via the second conductive material.

公开(公告)号：US07146221B2

公开(公告)日：2006-12-05

申请号：US09992248

申请日：2001-11-16

Applicant: Peter Krulevitch ,  Dennis L. Polla ,  Mariam N. Maghribi ,  Julie Hamilton

Inventor： Peter Krulevitch ,  Dennis L. Polla ,  Mariam N. Maghribi ,  Julie Hamilton

IPC: A61N1/05

CPC classification number: A61N1/0543 ,  H05K1/118 ,  H05K3/205 ,  H05K3/4007 ,  H05K2201/0162 ,  H05K2201/09481 ,  H05K2203/0733 ,  Y10S623/90 ,  Y10S623/901 ,  Y10S623/905 ,  Y10S623/926 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49139 ,  Y10T29/49147 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T29/49169 ,  Y10T29/49224

Abstract: An image is captured or otherwise converted into a signal in an artificial vision system. The signal is transmitted to the retina utilizing an implant. The implant consists of a polymer substrate made of a compliant material such as poly(dimethylsiloxane) or PDMS. The polymer substrate is conformable to the shape of the retina. Electrodes and conductive leads are embedded in the polymer substrate. The conductive leads and the electrodes transmit the signal representing the image to the cells in the retina. The signal representing the image stimulates cells in the retina.

公开(公告)号：US20060270211A1

公开(公告)日：2006-11-30

申请号：US11419887

申请日：2006-05-23

Applicant: Junichi Nakamura ,  Yuji Kobayashi

Inventor： Junichi Nakamura ,  Yuji Kobayashi

IPC: H01L21/82 ,  H01L21/4763

CPC classification number: H05K1/115 ,  H01L21/4857 ,  H01L21/563 ,  H01L21/6835 ,  H01L23/49816 ,  H01L24/16 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/97 ,  H01L2221/68345 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81001 ,  H01L2224/81192 ,  H01L2224/81801 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/15311 ,  H05K1/116 ,  H05K3/205 ,  H05K3/28 ,  H05K3/3473 ,  H05K3/4007 ,  H05K3/421 ,  H05K3/423 ,  H05K3/4644 ,  H05K2201/0376 ,  H05K2201/09481 ,  H05K2201/0949 ,  H05K2201/09509 ,  H05K2203/0338 ,  H05K2203/0361 ,  H05K2203/1536 ,  Y10T29/49126 ,  Y10T29/49144 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A method of fabricating a wiring board characterized in comprising a first step of forming a first solder resist layer on a support board and forming a first opening portion at the first solder resist layer, a second step of forming an electrode at the first opening portion, a third step of forming an insulating layer on the electrode and forming a wiring portion connected to the electrode at the insulating layer, a fourth step of forming a second solder resist layer on the wiring portion and forming a second opening portion at the second solder resist layer, and a fifth step of removing the support board.

Abstract translation: 一种制造布线板的方法，其特征在于包括在支撑板上形成第一阻焊层并在第一阻焊层形成第一开口部分的第一步骤，在第一开口部分形成电极的第二步骤， 在所述电极上形成绝缘层并形成与所述绝缘层上的所述电极连接的布线部分的第三步骤;在所述布线部分上形成第二阻焊层并在所述第二阻焊层形成第二开口部分的第四步骤; 层，以及除去支撑板的第五步骤。

公开(公告)号：US07105918B2

公开(公告)日：2006-09-12

申请号：US10923588

申请日：2004-08-19

Applicant: Teck Kheng Lee

Inventor： Teck Kheng Lee

IPC: H01L23/04

CPC classification number: H01L23/13 ,  G06F1/18 ,  G06F1/183 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/4985 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L25/0655 ,  H01L25/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/2919 ,  H01L2224/32013 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/83385 ,  H01L2224/8385 ,  H01L2924/00014 ,  H01L2924/01002 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/12041 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/351 ,  H05K1/0271 ,  H05K1/0284 ,  H05K3/3436 ,  H05K3/4007 ,  H05K2201/09036 ,  H05K2201/09045 ,  H05K2201/09481 ,  H05K2201/10719 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Various embodiments of an interposer for mounting a semiconductor die, as well as methods for forming the interposer, are disclosed. The interposer includes flexible solder pad elements that are formed from a core material of the interposer, such that the interposer may absorb thermally induced stresses and conform to warped or uneven surfaces. Embodiments of electronic device packages including a semiconductor die mounted to and electrically connected to the interposer, as well as methods for forming the electronic device packages, are also disclosed. In one electronic device package, the semiconductor die is electrically connected to the interposer with wire bonds attached to a routing layer of the interposer. In another electronic device package, the semiconductor die is electrically connected to the interposer by bonding the semiconductor die to the flexible solder pad elements of the interposer in a flip-chip configuration. A computer system incorporating an electronic device package with an interposer according to the present invention is also disclosed.

Abstract translation: 公开了用于安装半导体管芯的插入件的各种实施例以及用于形成插入件的方法。 插入器包括由插入器的芯材料形成的柔性焊盘元件，使得插入器可以吸收热诱导的应力并且符合​​翘曲或不平坦的表面。 还公开了包括安装到内插器并且电连接到插入器的半导体管芯的电子器件封装的实施例以及用于形成电子器件封装的方法。 在一个电子器件封装中，半导体管芯通过连接到插入器的布线层上的引线电连接到插入器。 在另一个电子器件封装中，半导体管芯通过以倒装芯片配置将半导体管芯连接到插入器的柔性焊盘元件而电连接到插入器。 还公开了一种结合根据本发明的具有插入器的电子器件封装的计算机系统。